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AN10861 greenchip iii tea1752 integrated pfc and flyback controller rev. 01 ? 16 july 2010 application note document information info content key w ords gree nchi p iii, t e a1 752 , pfc , flyback, high ef fi ciency, ada pto r , no te book, pc p o wer ab stra ct the t ea175 2 i s a membe r of th e new ge neration o f pfc a n d fl yb ack co mbina t i on controll er ics, u s ed fo r e f fici ent swi t ch ed mode po wer su ppl ies. it h a s a h i gh le ve l of i n te gration wh ich all o ws th e d e sign o f a co st-ef f ective po wer su ppl y with a mini mu m nu mb er of externa l co mpone nt s. th e t ea175 2 is fab r i c ated in a sili co n on insul a to r (soi) process, enabling it to o perate a wide voltage range. http://
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 2 of 46 cont act information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller rev i si on hi st ory rev date des c ription 01 20100716 first issue
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 3 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 1. introduction th e tea175 2 is a comb ina t io n co ntro ller with a pfc a nd flyb ack con t r o lle r integ r ate d i n to a n so-1 6 p a cka g e . both contr o ller s o per at e in quasi- re so na nce (qr) mod e and in disc o ntinuous c o nduction mode (dcm) with valley detec t ion. bo th cont rollers are switche d ind epe nd ently . th e pfc o u tput powe r is on -time con t r o lle d fo r s i mplicity . it is not necessary t o sense t h e p hase of the ma ins volt a ge. t he flyb ack outp u t po we r is cu rr en t mod e co ntro lled fo r goo d sup p r e ssio n of th e inpu t volt a g e r i pp le. th e commu nication cir c u i tr y b e tween the co ntro ller s is in te gr ated a nd no adju s tme n t is n eed ed. th e volt ag e an d cu rr en t levels men t i one d in this a pplica t io n note a r e typical value s . a d e t a ile d de scr i ption of the pin le ve l sp re adin g can be fo und in th e tea175 2t_ l t d a t a sheet . 1.1 s cop e th is a pplicatio n note de scr i be s the fun c tion a lity of th e t ea17 5 2 an d th e ad jus t m e n t s n eed ed within the p o wer con v e r ter app lication. the lar g e sign al p a rt s of th e pfc a nd the flyback power st a ges, th e desig n and th e dat a fo r the c o il an d th e tra n sfo rm e r ar e de alt wit h in a s e p a r a t e a p p lic at io n n o t e . 1.2 the tea1752 greenchip iii controller th e featur es of the gre e n c h i p iii allow a po we r supp ly e ngin e e r to design a relia ble , cost-ef f ectiv e and ef ficient sw itched mode powe r supp ly with a minim u m nu mbe r of e x ter n a l com pon en t s . 1.2 . 1 k ey fe atures ? pfc and flyba c k co ntro ller in tegr ated in o n e so-1 6 p a ckag e ? switch ing fre que ncies of pf c an d fl yb ack ar e ind e p end ent of each o t h e r ? no exter nal ha rd wa re r e q u ir ed for the co mmu nication b e twe en b o th co ntro ller s ? high le ve l of in te gr ation , re sulting in min i mal e x ter n a l com pon en t coun t ? integ r a t e d ma in s volt a ge en ab le and bro w nou t pr otection ? fa st latch re se t fun c tion im plem ented 1.2 . 2 s yste m features ? safe rest art mode for syst em f a ult conditions ? hig h vo lt ag e st a r t- up c u r r e n t so u r ce ( 5 . 4 ma ) ? reduct ion of h v current source ( 1 ma) in sa fe r e st ar t mo de ? wide v cc ra nge ( 3 8 v ) ? mosfet driv er volt age limited ? easy co ntro l o f st ar t- up b e h a vior a nd v cc circ uit ? gene ra l p u r pose in put fo r latche d pro t ectio n
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 4 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller ? inter n a l ic o v e r tem per atur e pr otection ? one h i g h - v o l t a g e sp ace r be twee n th e hv p i n and th e next active pin ? open p i n pr otection on th e vinsense, vosense, p f caux, fb ctrl and fbaux pin s 1.2 . 3 p fc featu r e s ? du al ou tp ut vo lt a g e b o o s t co nv er te r ? qr /dc m operation w ith valley sw itching ? fr eq uen cy limit a t io n ( 2 50 khz) to r e d u ce switching lo sse s an d electrom agn etic in te rf er en ce (emi ) ? t on c o ntrolled ? ma ins inpu t volt a ge comp en sa tio n fo r con t r o l loo p fo r go od tra n sien t r e spon se ? ov ercurrent protection (o cp) ? sof t st art an d so f t stop ? open /sho rt de te ction fo r pfc fee dba ck lo o p : no exter nal ove r volt a ge pr otectio n ( o vp) circuit ne ce ssar y ? adju st able d e la y for tu rnin g of f the pfc 1.2 . 4 f ly back fe atures ? qr /dc m operation w ith valley sw itching ? fr eq uen cy redu ctio n (fr) with fixe d minim u m pe ak cu rr ent and valley switch ing to ma int a in high e f ficien cy at low o u tpu t power le ve ls with o u t audib l e noise ? fr eq uen cy limit a t io n (1 25 khz) to reduce s witching los ses and emi ? cur r e n t m ode co ntro lled ? ov er cu rr en t pr ot ect i on ? sof t st art ? acc u rate ovp through auxiliary winding ? t i me- out pr otection for o u tput over load s a nd op en flyback fee d b a ck loo p , availab l e as safe r e st ar t (t ea1 7 5 2 t) o r latche d (tea1 752 l t ) pr otection 1.3 a pplication schematic fig u r e 1 shows the complete functional sc hematic of the tea1752 application.
x xxx xxx xxxx xxx xxxx xxx xx xxxx xxx xxxx xxx xxxx xxx xxx xxx xxx x x x x x xxxx xxx xxxx xxx xxxx xxx xxxx xxx x x xxxx xxx xxx xxxx xxx x xx xx xx xxx x xxx xxx xxxx xxx xxxx xxx xxxx xx xxx xxxx xxx xxxx xxx xx x xxx xx xxxx xxx xxxx xxx xxxx xxx xxx xxxx xxx xxxx xx xxxx xxx xxx x x x xxx xxx xxxx xxx xxxx xxx xxx xxx xxx xxxx xxx xxxx xxx xxxx xxx xx xxx xxx xxxx xxx xxxx xxx xxx xxxx xxx xxxx xxx xxxx xxx xxx xxxx xx xxxx xxx x x xxx xxx xxxx xxx xxxx xxx xxxx xx xxx xxxx xxx xxxx xxx x xx x AN10861 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 16 july 2010 5 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller fi g 1. app lic a t io n sc he ma tic + ? mains inlet c12 c15 r24 c16 c17 c18 c19 u1 pfctimer gnd la tch vinsense hvs v osense fbdriver fbsense hv v cc pfcsense pfcdriver pfca ux c20 c21 c22 c24 c25 r4 r25 r26 rt 2 ntc c14 c10 c23 c4 r7 r10 c6 r11 r27 r28 r29 q3 r3 r12 r9 c5 c2 c1 bd1 lf2 lf1 f1 r t1 ntc cx1 r1 r2 d1 bc1 r6 r14 r13 d4 d3 q2 r6a r18 r15 r17 r5a r5 r16 r16a q1 r8 d2 7 1 9 12 tea1752 c13 r20 r37 r38 r35 r34 fbctrl fba ux pfccomp r23a r23 d23a d5 c9 c8 c3 t1 l2 l1 5 1 4 2 6 c35 c34 r36 u2 u4 1 2 4 4 14 11 12 8 7 15 9 1 3 10 16 1 25 3 6 3 019aaa027 cy1 bc2 u3 v cc c30 r30 q4 r32 c27 c28 c29 r33 c31 l3 d30 11 7, 8 9, 10 8 2 3 5 6 7 driver srsense v out + v out ? n.c. n.c. n.c. n.c. 41 gnd tea1791 optional see section 5.2, 5.2.1
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 6 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 2. pin description t a bl e 1. pin des cri pti o n pin name fu nc tio n a l de scr ip tio n 1v cc supp ly vo lt a ge: v st a r t u p = 22 v , v th (uvl o) = 15 v . at mains switch-on, the capacitor connected to this pin is charged to v startup by the internal hv current source. when the pin voltage is lower than 0.65 v, the charge current is limited to 1 ma to prevent overheating of the ic if the v cc pin is short-circuited. when the pin voltage is between 0.65 v and v th(uvlo) , the charge current is 5.4 ma to enable a fast start-up. when it is between v th(uvlo) and v startup , the charge current is limited to 1 ma again to reduce the safe restart duty cycle. this results in a redu ction of the input power during fault conditions. when v startup is reached, the hv current source is pinched off and v cc is regulated to v startup until the flyback starts. see section 3.2 for a co mp lete descrip ti on of the st art-u p se que nce. 2 g nd gro und con nection . 3 f bc trl c on trol i nput fo r flyba c k for d i rect co nnection o f the optoco uple r . at a co ntrol vo lt a ge of 2 v the flyback deli v ers maximum p o wer . at a control volt age o f 1.5 v the flyba c k en te rs the fre quen cy red u cti on mode . at 1.3 v the fl yback stop s switchi ng. t here i s an i n te rnal 30 a current source conn ecte d to the pi n, wh ic h is co ntrolle d by the i n te rnal lo gic. t h is current source can be u s ed to i m p l emen t a ti me-out fun c ti on to d e tect an o pen control l oop or a sho r t circui t of th e out pu t volt ag e. t he time-ou t function ca n be di sable d with a re sisto r of 100 k betwe en th is p i n and g r ound . 4 f baux input from auxi liary win ding fo r tra n sfo r me r de magne ti za ti on detection , main s de pen dent ove r po wer protecti on (opp) an d overv o lt ag e pro t e c tio n (ovp) of the flyback. th e combina t i on of the d e magne ti zati on de tectio n a nd the vall ey d e tecti on at p i n hv determine s the switch-on momen t of the flyb ack in the val l ey . a flyback ovp is detected at a curre nt hi gher than 30 0 a to the fbaux pin. inte rnal filterin g prevents fal s e detecti on of an ovp . t he flyback opp st a r t s at a cu rre n t lo wer th an ? 10 0 a from th e fbaux pin. 5 l a t ch ge neral p u rpose la tch ed protection in put. wh en v st ar tup (o n pin 1) is re ache d, this pin i s cha r g ed to 1.3 5 v b e fo re the pfc an d th e flyb ack can b e ena bled . th e latched p r o t e c tio n is trigg e red whe n the p i n is pul led be low 1.25 v and the pfc an d th e flyb ack a r e disa bled . an internal 80 a curren t source is co nnected to the pi n, whi c h i s controll ed by th e interna l l ogic. because of th is cu rre n t sou r ce, a neg a tive t e mperature co ef fi cient (ntc ) re si sto r f o r te mp e r a tu r e pr ot ect i on can be d i rectl y con nected to th is p i n. 6 p fc comp fre quen cy compe n sation p i n fo r the pf c co ntro l loop . 7 v insense sense in put fo r main s vol t ag e. t h is pi n h a s five f unctio n s: ? main s en able l e vel: v st ar t ( vinsen se) =1 . 1 5 v ; ? main s stop leve l (b ro wnout): v sto p ( v i n sense) =0 . 8 9v ; ? main s volt ag e co mpensa t io n fo r the pfc con t ro l l oop ga in ba ndwid th ; ? fast lat ch reset: v flr =0 . 7 5v ; ? dua l boo st switchover poi nt: v b s t ( du al ) =2 . 2 v . th e volt age on pi n vinsense must b e an a v erage d dc valu e, re presentin g the ac l i ne vol t ag e. t he pi n is n o t us e d fo r sen s i ng the pha se o f the mains volt age .
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 7 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 8 p fc au x i nput from an au xilia ry win din g of the pfc coi l for de ma gne tiza tio n ti mi ng and va lley detectio n to control pf c swi t ch ing. the auxil iary wind i ng ne eds to b e co nne cted via a 5 k series resistor to preve nt da ma ge to the i npu t beca u se of l i ghtni ng surges. 9 v osense sense in put fo r the ou tput volt ag e o f the pfc. vosense pin , ope n-loo p and sho r t circuit detection: v th( o l)( vo sense) =1 . 1 5v ; reg u latio n of the pfc o u tp ut vo lt a ge: v re g( vo sense) =2 . 5 v ; pfc sof t ovp (cycle-by-cycle): v o vp( vo sense) = 2 . 63 v ; con t rol o u tput for the out pu t volt age o f the pfc: - d ual bo ost curren t : i b st(du al) = ? 15 a. 10 f b sense curren t sense i nput fo r flyback. at this pin the sum of three volt ages across three r e sistors is measured. sele ctin g th e prope r resistor value s: ? prevent s or min i mizes th e ri sk of saturation of th e flyb ack t r ansformer; ? allo ws some ad justment for en abling or disab ling the pf c; ? allo w s a system tha t ope rate s l i ne volt ag e inde pend ent ly . the m a ximum setting level for v se ns e( fb) m a x is 0.63 v a t dv/d t = 0 m v/ s. the level of v sen se ( fb )m in is 0.30 v at dv/d t = 0 mv/ s and is rela te d to the fixed pea k curre nt throu gh th e flyb ack transformer whe n the flyba ck is runn ing in f r equ ency re duction mod e . t here are two in tern al current sources conn ected to thi s pi n, i st ar t(s o f t )f b and i ad j(fbsense) . i st a r t ( so f t )fb i s an i n terna l cur r ent so urc e of 6 0 a, which is controll ed by th e intern al log i c. t he current so urce is used to i m plemen t a sof t st a r t fu nction for the flybac k. t h e flyba ck o n ly st art s wh en the interna l current so urce can charg e th e sof t st a r t cap a ci to r to a vol t ag e of mo re tha n 0.63 v . the r efo r e a minimum sof t st art r e sistor of 16 k i s req u ired to g uaran te e th e ena bli ng of the flyback. the current source i a d j( fbsense) is 3 a. it is in te nded to su pport the adj ustmen t for enab ling a nd disa blin g th e pf c. 1 1 pf cs ens e o verc u rr en t pr ot ect i on in pu t fo r p fc . th is inpu t is used to limit the maxi mu m pe ak cu rre n t i n the pf c co re. t he pfcsense is a switching - cycle - by-swit ching - cycle p r otecti on. w hen it reach e s 0 . 5 2 v at dv/d t = 50 mv/ s the pfc m o sfet is switched of f. an internal 60 a cu rre n t sou r ce is conn ecte d to this pin , which is controll ed by th e interna l l ogic. thi s curre nt sou r ce i s use d to impl ement a so f t st art and so f t stop function for the pfc to prevent aud ible n o ise. the pf c only st art s w h e n th e i n te rn al cu rre nt so u r ce can char ge the sof t st art cap a citor to a vol t ag e of more tha n 0.5 v . a so f t st a r t resistor o f at le ast 12 k is req u ired to g uaran te e th e enab ling o f the pfc. 12 pfc driver g a t e d r i ver o u tput for pfc mosf et . 13 f b d r iver ga te d r i ver o u t put for f l yback mosf et . t a bl e 1. pin des cri pti o n ?continued pin name functional description
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 8 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 3. system descripti on and c a lc ula t ion 3.1 p fc an d flyb ack st art conditions figure 2 and figure 3 show the conditions for enabling the pfc and the flyback. if start-up problems occur these conditions can be checked to find the cause of the problem. some of the conditions are dynamic signals (see figure 4 ) an d sh ou ld be c h e cke d wit h a n os cilloscope. 3.2 s t a rt-up sequence at switch -o n with a lo w ma ins vo lt age the tea175 2 po we r supp ly ha s the fol l owing st ar t- up se que nce (see figu re 4 ): 1 . th e hv cur r e n t sou r ce is se t to 1.0 m a an d th e v cc elca p is char ge d to 0.65 v to d e tect a p o ssib le shor t circu i t at pin v cc . 2. at v cc = 0.6 5 v , the hv cu rr en t sour ce is set to 5 . 4 m a a nd the v cc elc a p is qu ick l y ch ar ge d to v th( u vl o) . 3. at v cc = v th ( u v l o) , the hv cu rr ent so ur ce is set to 1 . 0 m a a gain a n d the v cc elcap is ch ar ge d t o v st a rtu p . 4. at v st a r t u p , th e hv cur r e n t so urce is switch ed o f f an d th e 80 a la t c h pin cur r e n t source is swit ched on to charge t h e la tc h pin cap a citor . at t h e s a me time the pfcsense and fbsen se sof t st art cu rrent sources ar e switched on. 14 pfc t imer t i mer pin to del ay the turni ng of f o f the pfc whe n th e load o f the fl yback is removed or minim i zed. th e pfc is ena bled wh en the volt age a c ro ss this pin i s lo w ( 1.27 v). it is disa bled when the volt age is hi gh ( 3.6 v ). 15 hvs hig h-volt age safety sp acer , no t conn ecte d. 16 hv hig h-volt age i nput fo r the in tern al st a r t-up curren t source (ou t p u t at pin 1) and va lley sensi ng of the flyba c k. th e combina t i on of the d e magne ti zati on de tectio n a t the fbaux pin a nd the vall ey d e tecti on at the h v pi n dete rmine the switch-on moment of the flyback in the valley . t a bl e 1. pin des cri pti o n ?continued pin name functional description fig 2. pfc start co nd iti on fi g 3 . fl yb ac k s t a r t c on di t io ns and latch > 1.35 v pfcsense (soft start) > 0.5 v vinsense > 1.15 v v osense > 1.15 v pfccomp > 3.5 v enab le pfc 019aaa02 8 f s w(fb)s w on(pfc) > 86 khz 019aaa02 9 and la tch > 1.35 v fbsense (soft start) > 0.63 v v osense > 1.15 v fbctrl < 4.5 v enable flyback
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 9 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 5 . whe n th e la t c h pin is ch ar ged to 1 . 3 5 v the pf c an d the flyb ack can st a r t swit ch ing , b u t o n l y wh e n th e v i nsen se p i n ha s re ac he d a lev e l o f 1. 15 v . 6. f o u r e x t r a co nd itio ns ha ve to be me t f o r en a b lin g t h e pf c: t h e s o f t s t ar t ca p a cito r at p i n pf csense m u st b e ch ar ged to 0.5 v , the volt a ge on th e vosense pin m u st be g r ea te r tha n 1.15 v , th e cap a cito rs co nn ecte d to th e pfccomp pin shou ld be cha r g ed to 3.5 v a n d f sw (f b) sw on( pf c) m u st be gre a ter th an 86 khz. remark: t he last co ndition is au to matically met by the tea175 2 du ring (initia l ) st ar t- up . t h is can b e me asur ed at th e pfctimer pin . it is in tern ally for c e d d o wn to a low volt age, w h ic h means th at th e pf c is en a b le d. 7. the sof t st art cap a citor at pin fbsense must be charged to 0. 63 v and the volt age o n pin fbctrl mu st be lo we r than 4 . 5 v to en able th e flyb ack. no rm ally , the vo lt age on p i n f b ct rl is low e r t h an 4 .5 v at th e fir s t f l yb ac k sw itch in g c ycle , un les s t h e fbctrl pin is o pen . whe n th e flyba c k st a r t s , the fbctrl tim e - out cu rr en t so ur ce is swit ched on. 8. whe n th e flyb ack h a s r e a c h ed it s nom inal ou tput vo lt ag e, the v cc su pp ly of th e ic is t a k e n over by the auxiliary winding. if the fl ybac k feedback l oop signal is mis s ing, the time- o u t p r otection a t the fbctrl pi n is trig ger ed , bo th co nver te rs ar e switch ed o f f, v cc dr op s to v th (uv l o) an d th e ic continu e s with step 3 of th e st ar t- up cycle . t h is is the safe rest art cy cle.
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 10 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e char ge time o f the sof t st art cap a cito rs can be ch osen in dep end en tly fo r the pfc and the flyback, b a sed o n th eir valu es. 3.3 v cc cycle in safe rest art protection mod e in safe re st art mod e the con t r o lle r go es thr o u gh the step s 3 to 8 as de scr i bed in section 3 .2 . fig 4. s t art-u p se qu enc e at lo w mains v o lt a g e v cc la tch pr o tection pfcsense pfcdriver fbsense fbdriver fbctrl v osense v o charging v cc capacitor star ting con v er ters nor mal oper ation protection restar t soft star t soft star t i hv v star t(vinsense) v to(fbctrl) v star tup v th(uvlo) v tr ip v en(la tch) v start(fb) vinsense 019aaa030 pfccomp v en(pfccomp)
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 11 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 3.4 m ains volt age sensing and brownout the mains input voltage is measured thro ugh the vinsense pin. when the vinsense pin has reached v start(vinsense) (1.15 v) the pfc can start switching, but only if the other start conditions are met as well, see section 3.1 . as so on a s the volt a ge on p i n vinsense drop s below v s t o p ( vi n se n s e) (0.89 v ), the pfc st op s s witching. the fly b ack however , continues sw itching until it s m a xim u m o n - t im e pr ot ec tion , t on (f b ) ma x (4 0 s) i s trig ge red . when this pr otection is trigg e r e d , th e ic sto p s switch ing and en ters sa fe r e st ar t mo de . the voltag e on p i n vinsense mu st be a n aver age dc va lue, re pr esentin g th e main s in put volt a ge. t he syste m wor k s o p tima lly with a time co nst a n t of ap pr oximately 1 5 0 m s a t th e vins ense p i n . t h e hig h tim e co ns t a n t on pin vinsense pr even t s a fast r e st ar t o f the pfc af ter a main s dr op out, th ere f ore th e vo lt ag e at the vinsense pin is cla m pe d to 100 m v below the v st ar t ( v i ns ense ) le ve l. th is g uar an te es a fa st pfc r e st ar t a f te r re cover y o f the ma ins in pu t volt a ge. 3.4 . 1 d isch arg e of ma ins input cap ac itor the x-cap a citors in the elec tromagnetic co mp atibility (emc) input filtering must be d i scha rg ed with a tim e co nst a n t of < 1 second fo r sa fety r eason s ( s e e ref. 1 ). in a typ i ca l 90 w a d a p ter a pplica t io n with cx1 = 2 2 0 n f , th e re place m en t value r e sistor value r v is determined by: (1 ) wh er e: ? r= r 1 =r 2 fi g 5. v in s en se ci rc ui t r y 019aaa03 1 tea1752 vinsense gnd 7 2 mains inlet cx1 r1 c1 bd1 + ? r2 r3 r4 c20 r v r rr 3 r 4 + () rr 3 r 4 ++ - ---- ---- ---- --- ---- ---- ---- ---- - + =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 12 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller t h e va lu e of r v m u st be lo wer tha n or e qua l to the foll owing: 3.4 . 2 b rowno u t volt a ge adju s tment the rec t ified ac input volt age is measured via r1 a nd r2. ea ch resistor a l te rn ately sen s e s ha lf the sin e wa ve , so bo th r e sistors must have the sam e va lue . t h e aver age volt a ge sen s e d at th e co nne ctio n of r1 a nd r2 is calcu l ated with eq ua ti o n 2 : (2 ) th e v ( a c) br owno ut rms level is ca lcu l ated with equa tio n 3 : (3 ) wher e: v s t o p ( vi n se nse) = 0. 89 v at a b r o w nou t thr e shold of 6 8 v ( ac) and in co mplia nce with iec-6 095 0 chap te r 2.1.1 . 7 "discha r ge of cap a citor s in e quip m en t" ( re f. 1 ). example values are shown in ta b l e 2 . a v a lu e of 3 . 3 f for cap a c i tor c 2 0, w i th 47 k at r4 , g i ve s the r e comm end ed time co ns t a n t of ~1 50 m s at th e vinse n se p i n . 3.5 i n t ernal overtemp er ature protection (otp) th e ic ha s an inter nal temp er atur e pr otecti o n to pr otect the ic fr om over he ating b y o v e r loads at the v cc pin . whe n th e jun c tion tem per atur e excee d s the th er mal shut d o wn temp er atur e, the ic stop s switchin g. as lo ng as th e otp is active, the v cc cap a citor is not r e cha r ge d from the hv main s. th e otp circ uit is supp lied fr om the hv p i n if the v cc supply volt age is not suf f icie nt. th e otp is a la tch ed pr otection . 3.6 l a t ch pin th e la tch p i n is a g ene ra l pu rp ose inpu t pin , wh ich can b e u s e d to latch both co nver ters o f f. t he pin source s a bia s cur r e n t i o(la tc h) of 80 a for th e dir e ct con nection o f a n ntc. whe n th e volt ag e on this pin is pulle d be low 1 . 25 v , switch ing o f bo th co nver te rs is stopp ed imm edia t e l y a nd v cc st ar t s cycling be twe en the v th ( u v l o) an d v st a r t u p with out a r e st ar t. switchin g of f an d then switch ing o n th e main s in put vo lt ag e tr igg e r s the fast la tch reset c i rc uit and reset s t h e latc h (see section 3 .7 ). at st art- up, the la t c h p i n h a s to be ch ar ged to ab ove 1 . 3 5 v be fo re both co nver te rs can b e ena ble d . cha rging of the latch pin starts when v cc =v startup . r v c x 1 -- ---- ---- - - 1 22 0 nf ---- ---- ---- --- -- - 4. 55 m == t a ble 2. vin s en se co mp on ent va lu es cx1 r1 r2 r3 r4 22 0 nf 2 m 2m 56 0 k 47 k 33 0 n f 1 .5 m 1.5 m 82 0 k 47 k 47 0 n f 1 m 1m 1. 1 m 47 k v avg 22 -- ---- ---- ---- - - v acr m s ? = v brownout ac () 22 --- --- ---- ---- - - v stop vinsense () r v r 3 r 4 ++ () r 4 --- --- ---- ---- ---- --- ---- ---- ---- -- - =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 13 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller no inter n a l filter ing is pr esent at th e la tch pin. a 1 0 nf cap a citor m u st be p l aced be tw ee n t h is p i n a n d th e ic g nd p i n to pr ev en t fa lse t r ig ge r i n g , als o wh en th e l a t c h pin fun c tion is no t used . l a tch i ng o n app lica t ion ove r temp er atur e occu rs when the to t a l re sist an ce va lue o f the ntc and it s s e ries resistor drop s below the following: (4 ) th e op to co up ler trig ger s the latch if the dr iven op totran sistor co ndu ct s mo re tha n 80 a. 3.7 f ast latch reset switch ing o f f and th en switchin g on th e main s in pu t volt ag e r e set s th e latched pro t ectio n . af ter the m a in s inp u t is switched of f, th e volt ag e on p i n vinsense dr op s b e lo w v flr (0 .7 5 v ). th is t r ig ge rs th e f a s t la tch re se t ci rcuit, but do es no t r e set the la tch ed p r o t e c tion . af ter the ma ins inpu t is switche d on, th e volt ag e on pin vinsense r i se s again . the la tch is rese t when th e level ha s p a ssed 0.85 v . th e system re st art s when the v cc pin is ch ar ge d to v st a rtu p ( s ee step 4 o f section 3 .2 ). 4. pfc description and calculation t h e pfc o per ates in qr mod e or dcm mo de wit h va lle y de te ctio n to r e d u c e th e swit ch-o n los s es . t h e ma xim u m switchin g fre que ncy o f the pf c is limited to 250 k h z to r edu ce switch ing lo sse s . if nece s sar y , o ne or mor e valleys are skipp ed to keep th e fr eq ue n cy be low 2 5 0 k hz. th e pfc o f the tea1 752 is de sig n e d as a d u a l b oost co nver te r with two ou tp ut vo lt age le ve ls tha t ar e de pen de nt o n th e ma ins in put volt ag e ra nge . th e ad va nt a ge is tha t the o v e r a ll system e f ficien cy at low m a ins is imp r o v e d be ca use of th e re duction o f the pfc switching losses. in low and med i um po we r ad apte r s ( < 1 2 0 w ) the con t ribu tion of pfc switching losses to the tot a l loss es is relativ e ly high. th e du al outp u t volt a g e is co ntro lled b y a n in tern al cur r en t sou r ce of 15 a at pin vosense. as shown in fig u r e 7 , the mains input voltage measured at pin vinsense is used to control the internal current source. this current source, in combination with the resistors at pin vosense, sets the lower pfc output voltage. at high mains, the current source is switched off. therefore, the maximum pfc output voltage is not affected by the fi g 6. usa g e o f th e l a t ch pi n pr otec tio n tea1752 la tch c19 rt 2 41 u1 32 r26 019aaa03 2 5 2 gnd r ot p v prot latch () i ol a t c h () - --- ---- ---- ---- --- ---- ---- --- - 1. 25 v 80 a ---- ---- --- ---- - 15.6 k == =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 14 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller ac cu ra cy of th e cu rr en t sou r c e . in a ty pic a l ad ap te r with a pf c ou tp ut vo lt a g e o f 38 5 v ( dc) a t h i gh m a in s, th e p f c ou tp u t vo lt ag e is 250 v ( dc) at lo w m a ins. a vo lt age of 2 . 2 v at pin vinsense cor r e spon ds with a ma ins inpu t volt a ge of ap pro x imately 1 8 0 v (ac). the sma ll slop e at th e tr an sfe r fu nction en sure s a st ab le switch o v e r of th e pf c o u t pu t vo lt ag e with o u t hiccu p s . th e pfc is switched o f f to ensu r e hi gh ef ficie n cy d u r i ng low ou tp ut cu rr ent s an d st a n d b y ( no o u tput cu rr en t) . af ter switch -o f f th e bu lk elcap vo lt age d r o p s to . 4.1 p fc output power and volt age control t h e pf c of th e t ea17 5 2 is o n - t im e co nt ro lled , the r ef or e it is no t ne ce ssa ry to m e as ur e th e ma in s ph as e an g l e. t h e o n - tim e is ke pt co n s t a nt d u rin g the ha lf sine wave to o b t a in a go o d pow e r f a c t o r ( p f ) an d a cla ss-d mains harmonics reduction (mhr). th e pfc o u tpu t volt ag e is con t r o lle d thro ug h th e vosense pin . at th e vosense pin the r e is a tr an scon du ct a n ce er ro r am plifier wit h a re fe re nce volt ag e of 2.5 v . t he er ro r at the vosense pin is co nver te d with 8 0 a/v to a cu rr en t on p i n pfccomp . the vo lt age on p i n pf cco m p , in co m b in at io n with the volt ag e o n p i n vinsense, deter min e s the pf c on - t im e. f i g 7 . t r an sf er fu nc ti on of vin sen se vo lt ag e to du al b o o s t cu r r e n t a t vo sen se 019aaa033 2.2 v ? 15 a v vinsense i i(v osense) 0 line voltage 2
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 15 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller a network with one resistor and tw o c a p a c i tors at the pfccomp pi n is used to st abilize the pfc contr o l loop . t h e mathe m atical eq ua ti on f o r th e tr an sf er fu nc tio n of a bo o s t co nv er te r c o n t a i ns th e sq ua re o f t h e m a ins in put vo lt ag e. in a typical app lication this result s in a low regulation bandwid th for lo w main s inp u t vo lt age s a nd a h i gh r egu lation b and wid t h at high inpu t volt a g e . the r e sult mi gh t b e th at at h i gh ma ins in pu t volt a ges it ca n be d i f f ic ult to m e et th e mh r r e q u i re me n t s. th e t ea1 75 2 us es th e ma in s in pu t volt a ge me asur ed thr o u gh the vinsense p i n to co mpe n sate the con t r o l loo p gai n as a fu nc tio n of th e ma in s in pu t vo lt ag e. as a re su lt t h e g a in is co ns t a n t ove r th e en tir e ma in s in put vo lt ag e ra nge . th e volt ag e at th e vinsense pin m u st b e an ave r ag e dc valu e, r e p r ese n ting the ma ins in put volt a ge. t he syste m wor ks o p tima lly with a time co nst a n t of ap pr oximately 1 5 0 m s a t the vins ense pin. 4.1 . 1 s etting the pfc output volt age th e pfc ou tp ut vo lt age is se t with a r e sistor divider b e tween the pfc outpu t volt a ge an d the vosense pin. in no rma l m ode , the pfc ou tp ut vo lt age is re gu lated so that th e volt a ge on the vosense pin is eq ual to . fi g 8. pfc on -time c o n t rol v vinsense 7 tea1752 11 68 12 v pfcsense v/i transducer i 2 + ? + ? v m i discharge i charge v ? v + v r v s r q s v pfcdriver pfc oscillator v osc v alley detection v pfcaux v oltage compar ator r amp oscillator v v alley t on limiting circuit i comp v pfccomp compensation network c1 c2 r1 v ref transconductance amplifier current multiplier i 1 i 2 v p c s 019aaa034 v reg v osense () v =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 16 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller t w o resist ors of 4.7 m (1 %) can b e used b e tween th e bulk elcap a nd the vo sense p i n . t h e dim e ns ion i ng o f th e i bs t( du al ) current source ( ? 15 a) ha s be en a dap te d to th e u s e of the s e re sistor value s . with a re sistor value of 4 . 7 m for r5 an d r6 a nd 60 k to 62 k fo r r7 a uni ve rsal ma ins a dap ter h a s a pfc ou tp ut vo lt age o f a ppr oxima t e l y 38 0 v to 3 9 0 v at h i gh ma ins and 2 4 0 v to 250 v at low main s. th e re sistor r7 ( 1 %) be twe en the vosen se p i n an d gr oun d can be ca lcu l ated with equation 5 : (5) examp l e with a r e g u late d pfc o u tput vo lt ag e of 3 8 2 v : at low mains the 15 a c u r r e n t so ur ce i bs t( du al ) is active. the lo wer pf c o u tput volt ag e can b e ca lcu l ated with equa tion 6 : (6) examp l e for calcula t in g the lowe r pfc o u tput volt ag e: ? r5 an d r6 = 4.7 m ? r7 = 62 k th e function o f cap a citor c4 at th e vosense pi n is to filte r noi se a nd to pr even t false tr igg e r i n g o f th e pr ot ec tion m o de s be ca us e of m o sf et s witch in g no ise , m a ins su rg e ev en t s or ele c tr os t a tic dis cha r ge (esd ) ev en t s . f a ls e t r ig ge r i ng o f t h e v o v p ( vo sens e ) p r ote c tion can ca use au dible n o ise an d distur ban ce o f the ac main s inp u t cu rr en t. false fig 9. pfc o u tp ut volt ag e settin g vinsense 2.2 v 1.5 a v osense gnd 9 2 tea1752 c4 pfc stage d1 c3 v o(pfc) r5 r6 r7 place c4 and r7 as close as possib le to the ic 019aaa03 5 r7 r5 r 6 + () v reg v osense () v o pfc () v reg v osense () ? () ------- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- -- - = r7 4. 7 m 4.7 m + () 2.5 v 382 v2 . 5 v ? () --- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- -- - 62 k 1 % () == v o pfc () low r 5 r6 r7 ++ r7 ---- ---- ---- ---- --- ---- ---- ---- - - v re g v os e n s e () i bst dual () ? r7 ? () ? = v o pfc () low 4. 7 m 4.7 m 62 k ++ 62 k ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- -- - 2. 5 v1 5 a ? 62 k ? () ? 24 0 v ==
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 17 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller trig ge ring of the v th (o l)( v ose n se) pr otectio n causes a safe re st art c ycle. a time cons t a nt of 50 0 n s to 1 m s at th e vo sense p i n sh o u ld be su f f icie n t, wh ich re su lt s in a v a lu e o f 10 n f for cap a c i tor c 4 . it is advisab le to p l ace r7 an d c4 a s close as po ssible to the ic betwee n th e vosense p i n and th e ic gnd p i n. 4.1 .2 c alcu lation of the pfc sof t s t art and so f t stop c o mponen t s th e sof t st ar t a nd sof t stop are i m ple m en te d th ro ugh th e rc ne twor k a t the pfcsense pin . r ss 1 m u s t ha ve a m i nim u m v a lu e o f 12 k to en su re that the volt ag e v st ar t ( s o f t )p fc of 0 . 5 v is rea c hed to e nab le th e st ar t- up o f the pfc. se e section 3 .2 for a d e scr i ptio n of st ar t-u p . the tot a l sof t st art or sof t s t op time is: it is advised to kee p the so f t st ar t time o f the pfc sh or te r than th e so f t st ar t time o f the flyback. it is also ad vised th at the so f t st ar t time is kep t within a r ang e of 2 m s to 5 m s. with c6 = 10 0 n f an d r1 1 = 12 k , the tot a l s o f t st art time is 3.6 m s. 4.2 p fc demagnetizing an d valley dete ction th e pfc m o sfet is switch ed on a f ter the tra n sfor mer is de mag netized . the inter nal circui tr y con nected to the pfcaux p i n detect s th e end of the se co nda ry str o ke. it also d e tect s the volt ag e acro ss th e pf c mosfet . th e next p r im ary str o ke i s st a r ted whe n th e volt age across the pfc mos f et is at it s mini mum in order to reduc e switc h ing los ses a nd ele c tr oma gne tic inter f er ence ( e m i ) (valle y switchin g) . th e maximu m switching fr equ en cy of the pf c is l i mite d to 250 khz to r edu ce th e swit ching losses. if necess ary , one or more va lleys ar e skip pe d to ke ep the fre q u ency below 250 khz. if n o dem agn etization sign al is d e tecte d on p i n pfcaux, th e co ntro ller g ene ra te s a z e ro cu rr en t sign al (z cs) 5 0 s af ter the last pfc gate sign al. if n o valley sig n a l is de te cted o n th is pin , the con t rolle r ge ne ra te s a valle y signa l 4 s af te r de mag netization was de te ct ed . fig 10 . p fc so f t st ar t an d so f t sto p soft star t soft st op contr ol ocp 11 pfcsense 0.5 v i star t(soft)pfc 60 a q1 r ss1 c ss1 r sense 019aaa03 6 tea1752 t sof t sta r t 3r ss1 c ssi =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 18 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 4.2.1 d esign of the pfcaux winding and circuit it is advised to set the v o lt age on pin p f c a ux as high as pos sible, but still w i thin the a b solute ma xi mum volt a ge r a ting of 25 v . doing this improv es the valley detection at low r i n g i ng a m plit ud es . t a king in to acco un t it s a b so lut e ma xim u m ra tin g of 25 v , th e volt a g e on p i n pf caux mu st be set as high a s p o ssib le to gua ra nt ee valle y de tectio n at low r i ng ing a m plitud es. th e nu mbe r of tu rn s of th e pfcaux windin g can be ca lcu l ated with equa tio n 7 : (7 ) ? v pf caux is th e ab so lute maximu m ra tin g of th e pfcaux pin ? v lma x is the ma xim u m volt ag e acro ss the pfc pri m ar y wind i ng fi g 1 1 . p fca u x c i r c ui try 019aaa037 c1 c2 l1 l2 9 5 7 1 r27 q1 d1 c3 pfca ux gnd pfcdriver 12 8 2 tea1752 n aux _ max v pfcaux v lm ax --- ---- ---- ---- --- --- - n p v v lmax -- ---- --- ---- - n p ==
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 19 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e pfc o u tput vo lt ag e at the pfc ovp level de term ines th e maximu m vo lt ag e a c ross th e pfc primary winding and can be calculated with equation 8 : (8 ) when a pfc coil with a higher number of aux ilia ry turns is used, a resistor volt age divider can be plac ed betw een the aux iliary winding and pin pfcaux . the tot a l resis t ive value of th e div i de r sh ou ld be lo we r th an 1 0 k t o pr ev en t de la y o f the v a lle y de te ctio n b y p a r a s i t i c cap a cit a nce. th e po lar i ty of the sig nal at the pfcaux p i n m u st be r e v e r s e d co mp ar ed t o t h e pf c mosfet dr ain sign al. it is r e c o m m e nd ed t o ha ve a 5 k res istor betw een the pfc aux iliary w i nding and pin pfcaux to pr otect the pin ag ain s t electrical o v e r stress, for examp l e, d u r i ng lig htning su rg e ev en t s. t h is re sist or sh o u ld b e pla ce d a s close as possible to the ic to pr even t inc o rrect valley switching of th e pfc b e cause o f exter nal d i stur ba nces. 4.3 p fc protection modes 4.3 . 1 v osense overvol t age prote c tion ove r volt a ge can o c cur acro ss th e bu lk el ca p dur ing th e initial st art- up an d lar g e lo ad cha nge s. this over volt ag e is cau s e d by th e relative s low response o f th e p f c co nt ro l lo op. the pfc contr o l loop resp onse mu st be r e la tively slo w to gu ar ante e a goo d po we r factor a nd me et the mhr re qu ire m en t s . the ove r v o lt ag e prote c tion ( o vp) a t the vosense p i n limit s th e overvo lt ag e. wh en the v ov p( vos e nse ) level of 2.63 v is detec t ed, the pfc mosfe t is s witched of f immediatel y rega rd less o f the on -time setting . th e switchin g of th e mosf et r e ma ins blocked u n til th e vo lt age on pin vosense dr op s b e low 2.63 v ag ain. whe n th e re si stor between th e vosense pin a n d g r o und is op en, th e ovp is also triggered. th e pe ak volt a g e a c r o ss the bulk elcap g ene ra te d by th e pfc b e cau s e o f an over sh oot a nd limited b y the pfc ovp ca n be calcu l ated with eq ua ti o n 9 : (9 ) 4.3 . 2 v osense open and short pi n detect ion th e vosense pin, wh ich is sen s ing th e pfc ou tp u t vo lt ag e, h a s a n in te gr at ed p r ote c t i on circui t to detect an op en a nd sho r t cir c u i ted pi n . th is p i n ca n also sense tha t on e of th e r e sisto r s i n th e vo lt ag e divide r is o pen . th er efor e th e vosense pin is comp letely fail- sa fe. it is no t necessar y to add an extern al ovp c i rcuit f o r the pfc. a n i n t e r n a l c u r r e n t sou r ce pu lls the p i n down to be low th e v t h ( o l) (v osen se) detection level (1 .1 5 v ) whe n th e p i n is op en . when v t h ( o l )(v os en s e ) is detect ed, leve l s witching of the pfc and the fl y b ack mosfet s is b l ocked until the voltage on pin vosense rises to above 1.15 v again. v lm ax v ovp v osense () v reg v osense () - ---- ---- ---- --- ---- ---- ---- ---- --- - v o pfc () 2.63 v 2. 5 v - ---- ---- --- --- - v op f c () == v o pfc () peak v ovp v osense () v re g v os e n s e () ---- ---- --- ---- ---- ---- ---- --- ---- - - v o pfc () nomin al ? 2.63 v 2.5 v --- ---- ---- --- - - v o pfc () nom i nal ? ==
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 20 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 4.3 .3 v insense ope n pin de tection th e vinsense pi n, which sen s e s the m a ins inpu t volt a g e , ha s an i n tegr ated p r o t e c tio n circui t for d e tectin g a n o pen pin. an inter nal cur r e n t so urce p u lls the pin do wn to b e low v st o p ( v i n sens e ) ( 0 .89 v ) whe n th e pin is op en. 4.3 . 4 o vercurrent protec tion th e over curr en t pr otection l i m i t s the ma ximum cur r e n t thr o u gh the pfc mosf et a n d pfc co il. th e cu rr en t is m easur ed via a cur r e n t sen se resistor in ser i es with the mosfet so ur ce . t h e mo sf et is swit ch ed o f f imm e dia t e l y w h e n th e vo lt ag e at p i n pfc sense ex ceeds the v se ns e( pf c )ma x lev e l of 0. 52 v at d v /d t = 5 0 m v / s. th e ocp is a swit ching-cycle-by-s witc h ing-c y cle protection. it is rec o mmended t o t a ke into accoun t a ma rg in of 0.1 v to avo i d fa lse tr igge rin g of th e pfc ocp by s witching of the fly b ack. false trig ger ing o f the v s ens e( pfc ) ma x pr ot ect i on c a n cau s e distur ba nces to th e ac m a ins inpu t curr en t . it is als o ad vis e d t h a t a sm a ll c a p a cit o r be tw ee n 10 0 p f a n d 2 2 0 p f is p l ace d dir e c t ly at th e pfcsense p i n to supp re ss e x ter n a l d i stur ba nce. th e curr en t sen s e r e sisto r can b e ca lcu l ated with equa tion 10 : (1 0) wh er e: i p q r( pfc) max is the m a ximum pfc pe ak cur r e n t at the h i gh lo ad a nd low main s. th e maximu m pea k cur r e n t fo r the pfc o p e r a t in g in qu asi-r e son ant mod e can be ca lcu l ated with equation 11 : (1 1 ) wh er e: ? p o( max ) is t h e m a xim u m o u t pu t po we r of th e flyb a c k ? 1. 1 is a f a ct or to c o m p en sa te for the dead t ime between z e ro current in t h e pfc in ductor a t the e nd of th e second ar y stroke a nd the d e tectio n of th e first valle y in quasi- reso nan t m o de ? is th e expe cte d ef ficie n cy of th e to t a l co nv er te r at m a xim u m ou tp u t p o w er ? va c mi n is minimum mains input v o lt age. 5. flyback descripti on and calculation 5.1 f lyback output power control an i m po rt ant aspect of the tea1752 flyback system is that it waits un til the transformer is demagnetized and at least one valley has appeared before it is magnetized again for the next cycle. the fbaux pin detects demagnetiz ation via the auxiliary winding. the hv pin detects the bottom of the valley via the drain of the mosfet or the central tap of the primary winding. r ocp p f c () v sens e pfc () max v mi n ar g ? i pqr pfc () max -- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- - - 0.5 2 v0 . 1 v ? i pqr p fc () max - --- ---- ---- ---- ---- --- ---- ---- --- - == i pqr pfc () ma x 22p im a x () 1. 1 ?? va c min - ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- - 22 p om a x () -- ---- ---- --- ---- - 1.1 ?? vac min - ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- - - ==
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 21 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller the output power (p o ) of the flyback can be calculated with equation 12 : (1 2) wh er e: ? l p st and s for the p r im ar y ind u ct an ce o f the flyback tr an sfor mer ? i p st an ds for th e pe ak cur r e n t th ro ugh the flyba c k tran sfo rme r ? f s st an ds fo r op era t ing fre que ncy o f the flyback ? st an ds fo r the ef ficiency o f the flyba c k l p is se lecte d at the st ar t o f the desig n, so th e se ttin g of th e pr ima r y pea k cu rr ent contr o ls th e ou tp ut p o w e r . t h e switc h in g fr eq ue n cy is a r e su lt of e x te rn al ap p licat ion p a r a m e te rs and internal ic p a rameters . external application p a r a me ters ar e the tra n sfo r m e r tur n s r a tio, the pr ima r y in du ct a n ce, the d r a i n so ur ce ca p a cit a nce, th e inp u t volt a g e , the ou tput vo lt ag e and th e fe edb ack signal from the c o ntrol loop. in ternal ic p a rameters are the o scillator s e tting, the s e tting of the p eak curr en t an d the de tectio n of dem agn etiza t ion an d valley . another logical method of cont rolling the output power is k eeping the primar y peak c u rrent i p fixed and ch ang ing th e op er ating fr equ en cy . ou tp ut po we r a nd o per ating fr eq ue ncy a r e linearly related during this ty pe of co ntro l. th is me th od is usuall y on ly do ne a t low ou tp ut p o wer . in this a ppli c a t io n no te it is calle d "ope ra tin g in fr equ ency re duction mo de " (se e sec t ion 5 .1 .1 .3 ). th e inp u t volt a g e o f the flyback is me asur ed thr oug h pin fbaux and u s ed to imple m en t a n over power pr otecti on (opp). the opp kee p s th e maximu m outp u t p o wer o f the flyback co nst ant over th e inpu t volt a ge. th e flyb ack ha s a n accura te ovp cir c u i t. the over vo lt age is me asur ed thr oug h pin f baux. bo th co nt ro ller s ( f lyb a ck an d pf c) ar e swit che d o f f in a la tc he d pr o t ec tio n whe n a n over vo lt age is de te cte d . 5.1 . 1 three different op era t ion mod es of the tea1 752 at initial st art-up, the fly b ack always starts at the maximum output power. this means that the system starts up in the so-called quasi-resonant mode. the flyback of the tea1752 passes through three operation modes (see figure 12 ) from maximu m to min i mum outpu t po we r: ? quasi- re so na nt ( q r) mo de ? disco ntinu ous co nd uctio n mod e (dcm ? fr eq uen cy redu ctio n (fr) m ode dema gn etiza t ion detection and valley switching ci rcuitry inside the ic is active in all three different operation modes. p o 1 2 -- - l p i p 2 fs ?? ? ? =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 22 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 5 . 1 . 1 . 1 q uas i - r es ona nt mode th e flyb ack op er ates in qu a s i-r e son ant mo d e at h i gh and ma xi mum ou tput powe r . the o u tput po we r is con t r o lle d by th e pea k cur r e n t (see section 5 .1 ). a lo we r pe ak cu rr ent tha n th e maximu m allo we d va lue r e sult s in lower o u tpu t po wer a nd a hig h e r op er ating fre q u ency u n til th e maximu m ope ra tin g fr eq ue n c y is re ac he d. t h e q u asi- re so n a n t m o de can e a sily b e re co gnize d. t he ne xt pr imar y s witch ing cycle st ar t s whe n the bo ttom o f the first valley is detec t ed. the primary peak current (i p ) is set by the voltage on pin fbctrl. it is advised to place a 10 nf noise filter capacitor (c15) as clos e as possible to the fbctrl pin to avoid disturbance of the flyback by switching of the pfc mosfet. the voltage on pin fbctrl is measured back at the fbsense pin and can be calculated with equation 13 (only valid du r i ng q r m o de o r dcm ): (1 3) wh er e: ? v fb ctrl is a llow e d to va ry b e t we en th e 1 . 5 v an d 2 . 0 v (o nly v a lid d u r in g q r m o de or dcm mode) ? i a d j(f bse nse) is related to a current source inside the ic, connected to the fbsense pin ? resistors r16 and r17 can be found in the circuit diagram, see figure 13 . f i g 1 2 . f ly ba c k op era t io n mo de s v fbctrl 1.5 v pfc off 019aaa038 pfc on fr dcm qr f s w(max) (fb) flyback switching frequency v sense f b () 0. 66 v fbctrl i adj fbsense () r1 6 r 1 7 + () 0. 69 v ? ?
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 23 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e pe ak cur r ent i p th ro ugh the flyba c k tran sfo rme r is d e fine d by: (1 4) th e maximum pe ak cur r e n t i pma x is de te rm in ed by v s en s e( f b) m ax . r16a is not mentioned in eq ua tio n 14 , but this is explained in section 5.1.5 . usua lly the r equ ire d ou tp ut p o wer con t in ues to dr op a f ter th e initial st ar t- up . th is r e sult s i n th e flyb ack en te rin g the disco ntinu ous co nd uctio n mod e when th e maximu m switch ing fre q u ency is re ache d. 5 . 1 . 1 . 2 d isco ntinuo us co nduc tion mode in dcm th e o u tput po we r is re du ce d by a fur t her re duction of th e pe ak cu rr en t ( i p ) an d b y skippin g on e or mo re va lleys at the same time . in this m ode the switch ing fre q u ency i s kep t mo re o r less con s t ant. t he exact switch ing fr equ ency dep end s o n th e de te ction o f the valle ys, but it is never high er tha n the ma xim u m fre que ncy . th e outpu t po we r is decr ease d b y re ducin g the p eak cu rr ent a n d as a r e sult m o re valle ys a r e skippe d un til the volt a ge acr o ss fbctrl dr op s b e lo w 1.5 v . wh en this ha ppe ns th e o per ating m ode sh if t s fro m dcm to fr m ode . som e times th e dcm is not re ache d wh en the sele cte d pr imar y in duct a n c e va lue o f the tr an sfo r me r is to o la rg e. in such a sit u ation t h e flyback sk ip s the dcm when it is reducing power , it jump s direc t ly from the q r mode to t h e fr mode. 5 . 1 . 1 . 3 f r e que ncy r e duc tion mod e th e vo lt ag e a c ross the fbctrl pin i n fr eq uen cy re duction mo de no lo nge r set s the p eak cur r e n t. instea d it se t s the ope ra tin g fre q u ency . the minim u m pe ak curr en t ( i pmin ) thr o ug h the tr ansfor m er is kept co nst a n t du rin g th e fr mod e . th e ra tio between i pmi n a nd i pma x d epe nds mai n ly o n th e value o f the sen s e re sistor r s ens e , assum i ng that the cor e is no t satur a ted a t i pma x . th e outpu t p o wer is re duced by r educing the operating frequency and as a result more valleys are skipped. fbsense has two intern al referen c e level s : (1 ) v se n se( f b )m ax = 0 .630 v a t dv/d t = 0 m v/ s (2 ) v se nse ( fb )m in = 0 .3 00 v at dv/d t = 0 m v/ s fig 13 . m ost impo rt an t co mp on en t s fo r a d jus t in g the flyb ack in the a p p l icatio n c10 fbsense r16 l p q2 r sense r comp c23 r16a fbdriver r series = r17 + r16 v i (dc) r17 t1 c_output d_output 019aaa039 i adj(fbsense) i p v sense f b () i adj fbsense () r1 6 r 1 7 + {} r sense - --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- - - =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 24 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e ope ra tin g freq ue ncy of th e flyba c k du rin g fr mo de de term ines if the pfc is turn ed o n o r tur n e d of f. the tu rn -o n op er ating fr eq uen cy for en ab ling th e pfc is selected at a h i gh er r a te than the tu rn- o f f o p e r atin g fr eq uen cy . so the pfc is tur ned o n at a high er o u tpu t p o wer a nd tur ned o f f ag ain a t a lowe r outp u t p o wer . in ge ner al the o u tput vo lt ag e of an ad apte r is fixed, so a high er o r lower outp u t p o wer o f the flyback resu lt s in a h i ghe r or lower o u tput curr en t. th e over all ef ficie n cy o f the system is impr ov ed if the pfc is disab l ed a t low ou tp ut cu rr en t s . f o r th is re as on th e pfc is tur ned o f f ab ove 25 % of th e no mina l o u tput curr en t. on th e othe r ha nd, th e pfc is tu rn ed o n at la rg er o u tpu t cur r en t s in o r d e r to imp r o v e the p o wer factor o f the lin e cu rr en t. this is of te n don e be low 5 0 % o f the n o min a l ou tp ut current. the hysteresis between turning on and turning off the pfc depends on the primary inductance value, the output power and the line voltage. it is therefore important to select the right inductance value to ensure enough pfc-on/pfc-off hysteresis. section 5.1.2 d e scr i be s ho w this is d one . 5.1.2 the relationship between inductance value and the hysteresis of the pfc the tea1752 runs with a fixed minimum peak current (i pmin ) to control the output power during the frequency reduction mode, see section 5.1 (the value of i pmin is calculated in equation 17 ) . th er efore th e on- time ( c o ndu ctin g tim e of the mosfet) dep en ds o n th e sele cted i ndu ct a n ce value a n d the in pu t volt a ge, it is li nea rly rel a ted to th e ind u ct an ce valu e and inver s e l y pr op or tio nal to the in put vo lt ag e. t he re lation sh ip be twee n on -time a nd of f-time o f the mosfet is fixed via the tur n s r a tio of th e tra n sfo rme r an d the ou tp ut volt a ge ( neg lecting the in flu ence o f the r e lative ly s h ort valley time). at lower line v o lt ages the o per ating fr equ en cy and outpu t p o wer decre ase when a r e la tive ly lar g e p r ima r y inductance is selected, see also section 5.1 and figure 14 .
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 25 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e situ ation b e come s wor s e wh en the p r ima r y indu ct ance valu e is incr ease d as well , because this li mit s the max i mum deliv erable ou tput power at lo w line vol t age s even m o r e ( b y de fa ult flyb ack ru ns at a lower op era t ing fr equ en cy , a s sum i ng a fixe d p e a k cur r ent) . in p r actice th is me an s that th e flyb ack sup por t s a limited amount of pow e r at low line volt a ges. asking mor e p o wer activa te s the fe ed back loo p an d re sult s in en ab ling the pfc a t lo we r ou tput po we r tha n was or igina lly intend ed . in o t h e r wo rds, th e h y ster esis b e twe e n tur n in g on an d turn ing o f f th e pfc b e com e s sm aller at low line volt ag es in co m p ar iso n with typical lin e vo lt age s, a s su ming th at a re la tively large primary in d u ct an ce value for the tra n sform e r is se lected. wh en the se lecte d pr imar y in duct a nce va lue is much too la rg e, u n wanted syste m beh avior occu rs, b e cau s e th er e is n o hy ste r e s is lef t . t h e ma xim u m in duct a n c e va lue sho u ld be limited to pr event this unwanted s ystem behavior at l o w line volt a ges. mo st custo m er s p r e f e r a cer t ain min i mum h y ster esis b e twe en tur n in g on an d turn ing o f f the pfc at low line volt ages. so it is help fu l to ha ve an ind i cation of the accep t able ma xim u m pr imar y ind u ct an ce valu e o f the tr an sf o rme r at the st ar t of the de sign. no te that sever a l assump tio n s have to be m ade to calcula t e th ese ind u ct ance valu es i n figu re 1 5 . therefore these values should only be thought of as indications. fi g 14 . o p e ra tin g freq ue nc y a s a fu nc ti on o f (l ow ) li ne v o l t a g e s , as su min g a relative ly larg e selec te d pr ima r y ind u c t a n ce v a lue for th e fly b ac k tr an sform e r t p t s i s i s t p t = 1 / f s t s t s t x t + t x = 1 / f s-lo w t s t v alle y flybac k dr iv en at lo w line v oltages , assuming a relativ ely large pr imar y inductance f or the flybac k tr ansf or mer flybac k dr iv en at ver y lo w line v oltages , assuming a relativ ely large pr imar y inductance f or the flybac k tr ansf or mer i pmin (= fix ed v alue) i pmin (= fix ed v alue) t p t valley t p 019aaa040
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 26 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller fig u r e 15 shows an indication value for the primary inductance value of the flyback at different output powers and different turn ratios. selecting a larger value than proposed here can result in too much loss of hysteres is. selecting a smaller value prevents that, but causes more overall switching losses . the inductance values shown in figure 15 result s in los s of s o me hysteres is below roughly 1 1 5 v (ac) line volt age. however , they are us ually still accept able at 90 v (ac), as suming that the volt age across bulk elcap c3 does no t dr op t o o m u ch . a ru le of th um b is th at the valu e of th e bu f f er ca p a cito r c3 in micr ofar ads is u s u a lly se lecte d eq ual to the ou tp ut power in w a tt s. applyin g th is g ene ra l r u le o f thum b re su lt s in a m i nimu m vo lt age a c ross th e buf fer ca p a citor of a p p r oxima t e l y 100 v (dc) at 90 v ( ac) line vol t age a t 5 0 % o f the no mina l outpu t p o wer . selecting the induct ance v a lue with the help of fig u r e 15 is one method. another method is using equation 15 : (1 5) wh er e: ? i o(no m) st a nds for th e no mina l outp u t cu rr ent a ccor d in g to the type p l ate of the a d a p ter ? v o s t ands for the output volt age ? v f st and s for fo rwar d volt ag e acro ss the secon dar y d i ode ? l p st ands for the primary inductances of the flyback transformer l p =f ( p o ) assumptions: minimum volt age across the buf fer ca p a citor (c 3) is a pproxima t ely 100 v ( dc) a t 50 % of the nominal output pow er . (1 ) n (v o +v f )=8 0 v (2 ) n (v o +v f )=9 2 v (3 ) n (v o +v f ) = 104 .3 v (4 ) n (v o +v f )=1 1 8v (5 ) n (v o +v f ) = 130 v f i g 1 5 . i n di c a t i on of th e ac c e p t a bl e pr ima r y in du ct an ce va lu e, r e la te d t o o utp ut po we r an d n (v o + v f ) (1) (2) (3) (4) 019aaa041 p o (w) 75 155 135 115 95 400 600 800 lp ( h) 200 (5) l p nv o v f + () ---- ---- ---- ---- --- ---- ---- ---- - - ?? ?? ? () + () () ? =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 27 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller ? n is the tur n s r a tio b e twe e n the p r ima r y an d se co nd ary windin g s (n p /n s ) equation 15 gives so me de viation at a low an d a high va lue of the pr od uct. it is th er efor e re co mme nde d to ke ep this va lue be twe en 80 v a nd 13 0 v . examp l e: ? i o(no m) =4 . 6 2a ? v o =1 9 . 5v ? v f =0 . 0 5v ? =1 0 4 . 3 th e final value used is 450 h. 5.1 . 3 r elati onship b etwee n i pmin and th e required pfc-on/o ff level th e pfc is usua lly tur ned o n an d tu rn ed o f f betwee n 50 % and 25 % of the n o mi nal o u tput cu rr en t of th e flyb ack. th e pf c can o n ly be turned on or turn e d of f b y the flyback whe n it is run n in g in fr m ode . th e typ i ca l in tern al op er ating fre que ncy o f the flyback fo r tur n in g on the pfc is 8 6 khz a n d for tu rn ing of f th e pf c is 48 khz. using the aver age o f b o th va lue s ( per cent a ge wise an d fr eq uen cy wise ) in comb ina t io n with eq uatio n 1 2 results in equation 16 : (1 6) or: (1 7) wh er e: ? 0 . 3 75 is th e aver age va lue of 50 % an d 25 % of th e nom inal ou tput cu rr en t ? v o is the o u tput vo lt ag e ? v f is for w ar d vo lt ag e acro ss th e second ar y d i ode ? l p is the p r im ary ind u ct ance s of th e flyb ack tra n sform e r ? 6 700 0 is the a v e r a ge valu e of 8 6 0 0 0 h z a nd 48 00 0 h z ? fb is th e ef ficie n cy o f the flyb ack ( p le as e use r e latively high valu es, such a s 0. 97 ? 0. 98 ) example: ? i o(no m) =4 . 6 2a ? v o =1 9 . 5v ? v f =0 . 0 5v nv o v f + () nv o v f + () l p 1 04.3 1 04.3 ---- ---- ---- - ?? ?? 43 061 1 0 6 ? 4.62 1 9.5 0 . 05 + () () 1. 000 5 ? 47 6 10 6 ? h = = 0. 37 5 i o nom () v o v f + () 1 2 -- - l p i pm i n 2 670 00 fb = i pmin 20 . 37 5 i o nom () v o v f + () l p 670 00 fb --- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- - - =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 28 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller ? l p =4 5 0 h ? fb =0 . 9 8 5.1 . 4 the influenc e of r se nse and the series resi st ance r1 6 + r17 th e sense r e sistor , r se nse , to gethe r with th e se rie s imp eda nce r16 a nd r17 , ha s four func tions : ? pr event or m i nimize the r i sk of sa tu ra tio n of th e fly b ac k t r a n s f o r m e r . ? allow en oug h po we r to th e ou tp ut ( a ssumin g the ind u ct an ce is no t go ing in to saturation). ? allow some a d justmen t for e n a b ling o r disa bling th e pf c a t a cer t ain ou tput powe r lev e l. note that the value of r s ens e is mor e do mina nt fo r this a d ju stme nt tha n the valu es o f r16 a nd r17 , as their influen ce is mu ch sma ller . ? r1 7 an d c2 3 pr ev en t fbs e nse b e i ng c h a r ge d neg ative becau se of d i stu r ba nces ac ross r se ns e . the saturation level (i p(sat) ) of the transformer and the va lue of the sense resistor are important design parameters. section 5.1.4.1 s h o w s th e ca lcu l atio n fo r th e sat u r a t i on lev e l of the transformer . af ter th at th e ma xim u m pe a k cu r r e n t (i pma x ) th ro ug h th e tr an sfo r me r is d e t er m i ne d . t h is va lu e sh ou ld pr ef er ab ly be belo w the s a t u r a t i on le ve l o f the transformer . 5 . 1 . 4 . 1 c alcu la ting th e sa tura tion c u rre nt i p( sa t) of th e flyb ack t r a n sf ormer the saturation level of a transformer can be calculated with equation 18 . (18) examp l e with the fo llowing a s sum p tions: ? n p = 32 t ur ns ? b max = 3 90 mt ( p q32 20 , ma te ria l pc44 , b max a t 10 0 c) ? a e = 170 10 ? 6 m 2 ( f rom tr ansfor m er su pplie r da t a shee t) ? l p =4 5 0 10 ? 6 result: v a lues for a e an d b max can be fo und in th e dat a sh eet of th e tr an sfor me r su pp lier . th e b max value dep en ds o n temp er atur e. it decr eases r apid l y a t hig h op er ating tem per atur es. th er efor e th e b max va lue sho u ld be selected at high o per ating temp er atur es. satur a tion of the cor e doe s no t ha ppe n wh en the ma xim u m pea k cur r en t ( i pma x ) is below the s a turation cu rr en t (i p( sa t) ). sec t ion 5 .1.4.2 sh o w s th e c a lc ula tio n of i pma x . a saturated c o re does not de live r m o r e po we r t o th e ou tp ut , b u t o n ly d e te r i or at es th e ov er all pe rf or ma n c e o f th e sys tem (more st ress and emi and, wo rst case, a possible sys tem failure). i pmin 20 . 3 7 5 4.62 19 .5 0.05 + () 45 0 10 6 ? 67 000 0.98 --- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- --- - 1.51 4 a = = i ps a t () n p b ma x a e l p -- ---- ---- ---- --- ---- ---- ---- ---- --- - = i ps a t () 32 0. 39 170 10 6 ? 450 1 0 6 ? -- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- -- - 4.71 a ==
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 29 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 5. 1. 4. 2 c a l c u l at i o n o f i pma x for f l y b ac k ope rat i ng in quas i- res ona nt mode th e flyb ack pe ak cu rr en t op er ating in quasi- re so nan t mo de ca n be ca lcu l a t ed w i th eq ua tio n 19 : (1 9) wh er e: ? a=n v i(dc) min l p ? b= ? 2 i o l p {n (v o +v f )+v i(dc) min } ? c= ? 2 i o t va l l e y n v i( dc) min (v o +v f ) fo r a, b an d c: ? v o is the o u tput vo lt ag e ? n is the tur n s r a tio b e twe e n the p r ima r y an d se co nd ary windin g s (n p /n s ) ? l p is th e ind u ct a n ce v a lu e of th e pr im ar y w i nd ing ? t va ll ey is t h e valley t i me, s o metimes also desc ri be d as d e a d tim e . t h is time is usua lly ar o u n d th e 1. 1 s ? v i( dc) m in is th e min i mum volt a ge acr o ss b u lk e l ca p c3 at it s no mina l o u tpu t loa d . in this examp l e th is is 75 v ( dc). the a c tua l vo lt age dep end s o n how fast the pfc is e nab led. it is the r e f o r e r e com m en ded to che c k th is valu e in ever y a pplica t io n. examp l es: ? a = 5.333 3 75 45 0 10 ? 6 =1 8 0 10 ? 3 ? b= ? 2 4.6 2 45 0 10 ? 6 {5 .3 33 3 ( 19 . 5 + 0. 05 ) + 7 5} = ? 745 .3 9 10 ? 3 ? c= ? 2 4.62 1.1 10 ? 6 5.333 3 75 ( 19 . 5 + 0. 05 ) = ? 79 .4 82 4 10 ? 3 th e ca lcu l ated pe ak cur r en t is be low the sa tu ra tio n level o f 4.71 a ( see sect ion 5 .1.4.1 ). it is reco mmen d e d to h a ve some m a rg in be twe en this ca lcu l ated valu e an d th e sa tu ra tio n lev e l of the core. fo r example, the system might still r un into a problem during a peak lo ad. t h is is so methin g th at h a s to be checke d as we ll for the fina l d e sign. the calcula t io n b e low sh ows the r e sult s if the a s su med p eak ou tp ut cu rr ent is 5 . 7 a an d th e pfc h a s been on for some time. it is ass u med t h at th e minimu m vo lt ag e acro ss bu f f er ca p c3 is 240 v (dc). ? a 1 = 5 .3 333 240 45 0 10 ? 6 = 576 10 ? 3 ? b 1 = ? 2 5.70 45 0 10 ? 6 {5.33 3 3 (1 9. 5 + 0 . 0 5) + 24 0} = ? 1.766 1 ? c 1 = ? 2 5. 70 1. 1 10 ? 6 5. 33 3 3 240 (1 9.5 + 0 . 0 5 ) = -3 13.8 10 ? 3 i pmax b ? b 2 4ac ? () + 2a ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- - - = i pmax at i o 4.62 a = () = 745 .3 9 10 3 ? 74 5.39 ? 10 3 ? () 2 41 8 01 0 3 ? 79.482 4 ? 10 3 ? ? + 2 180 10 3 ? -- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- --- - 4. 25 a =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 30 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller sele ct the h i ghe st value of i pma x (at i o = 4 .62 a and at i o = 5 .7 a) an d co mp ar e th is va lu e with i p( sa t) . the valu e of i pma x sh ould pre f era b ly be lowe r th an i p( sa t ) . if so, t h en us e the valu e of i p( sa t) fo r i pma x , beca u se th is g i ve s mo re m a rg in to th e de live r a b le ma xim u m o u tput po we r . 5. 1. 4. 3 c a l c u l a t i o n o f th e cu rren t s e n s e re s i s t o r r se n se th e ne xt step is calcula t in g th e value for r sen se , s e e equa tion 20 : (2 0) rema rks: ? v se ns e( fb )ma x an d v se ns e( fb )mi n : mea sure d at dv/d t = 0 m v/ s. ? i pma x : fill in the highes t i pmax level (s ee sect ion 5 .1.4.2 ). using the sa tura ti on cu rr en t i p( sat ) fo r i pma x is of ten p r efe r r ed (a ssum ing that i p( sa t) >i pma x ) b e cause it gen er ally a llows for a slig htly h i ghe r ma xim u m ou tp ut power fo r the de sign ( i t g ive s some e x tr a mar g in ). using th e high est p eak curr en t of all (i p( sa t) =4 . 7 1 5 a , s e e sec t ion 5.1.4 ) results in a value for r sense as calculated in equation 21 : (2 1) 5.1 . 4 . 4 c alcu la tion of t h e s e ries r esist anc e r1 6 and r17 eq ua tio n 22 calculates the ser i es r e sist an ce o f r16 a nd r17 : (2 2) rema rks: ? v se ns e( fb )ma x an d v se ns e( fb )mi n : mea sure d at dv/d t = 0 m v/ s examp l e for a typical 90 w ada pter : t h e va lu e of r1 7 is o f te n a va lue r o u g h l y be twe e n 68 0 an d 12 00 . it s purpos e is to p r eve n t c1 0 bei ng cha r ge d in a n un wa nt ed wa y be cause o f spikes acro ss r se nse that may trig ge r the esd p r otection inside th e ic. se le ctin g a va lue b e tween th ese two limi t s a llows some fr ee dom for tr immin g r1 6 or th e dela y comp en sa tio n re si stor r1 6a. th e value of r17 is ch osen a t 1 000 . t he valu e of r1 6 th en b e come s: 485 04 ? 100 0 = 4 750 4 . i pmax at i o 5.7 a = () = 1.766 1 1 .766 1 ? () 2 4 576 10 3 ? 31 3.8 ? 10 3 ? ? + 25 7 61 0 3 ? -- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- - 3. 23 a = r sense v sense f b () max v se n s e f b () min ? i pmax i pmin ? ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- -- - 0.63 0.3 ? i pmax i pmi n ? -- ---- ---- --- ---- ---- ---- ---- - - 0.33 i pm ax i pmin ? - ---- ---- ---- ---- --- ---- ---- -- - = == r sense 0.33 4. 71 5 1.5 14 ? ---- --- ---- ---- ---- ---- --- ---- -- - 0. 10 3 0.1 00 == r series i pm a x v sense f b () min v sense f b () ma x ? i adj fb s e nse () i pmax i pm i n ? () - ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- -- - i pmax 0. 3 i pmin 0.63 ? 31 0 6 ? i pmax i pmin ? () -- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- -- - == r se ri es 4.71 5 0.3 1.5 14 0.63 ? 31 0 6 ? 4. 71 5 1.5 14 ? () -- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- - - 4 8504 = =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 31 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 5.1 . 5 c alcu lation of the dela y compe nsation re sistors r comp and r1 6a r comp an d r16a ar e inten ded to com pen sa te th e su m of th e fo llowing thr e e d e la ys: ? the internal delay time of t h e i c ? th e switch- o f f time of th e mosf et ? th e de lay time r e la te d to r1 7 c23 (filter in front of the fbsense pin). the transformer is still conducting current at th e primary side during the sum of all these delay times. this delay can be translated into an extra current, i delay , through the transformer (see figure 16 ) a nd r e sult s in e x tra en erg y for the o u tput. the amo unt of extra e ner gy dep en ds o n th e inp u t vo lt age . th e p u r pose of the resistors r comp and r16a is to co mpe n sate fo r the un wa nted cu rr en t (i del a y ) with the corr espo nd ing d e lay time. th e volt a ge a c r o ss r1 6a can b e tra n slated to a cu rr en t i pre set with th e cor r esp ond ing p r ese t time . the system is comp ensated if the pr e s et va lu es m a t c h th e de lay va lu es. th e volt ag e acro ss r16a de pen ds on the cur r e n t t h rough this res i stor . the main p a rt of this cu rr en t flows via r5, r5a, a nd r6a. no te th at th e cu rr en t thr oug h r5 an d r5 a i s split up in to t w o p a rt s af t e r w a r d s a n d is th er e f or e on ly p a rtly flo win g th ro ug h r6 . t h e oth e r p a r t is flowin g thr o u gh r6a. on e re sistor can r epla c e all thes e resistors. this res i stor is called r comp . th e value of th is r e sisto r can be ca lcu l ated with eq uation 2 3 whe n the sche m atic is built according to figure 1 : (23) examp l e calculatio n fo r a typ i ca l 90 w a d a p ter : f i g 1 6 . p rin c i p l e of de la y c o mp en sa ti on i dela y i preferred t preferred i preset t delay t preset 019aaa042 r co m p 2r 5 r 5 a r6a 2 - ---- ---- - - ++ ?? ?? r co m p 22 m 1.3 m 2. 7 m 2 ---- ---- ---- ---- -- - ++ ?? ?? 9. 3 m 930 0 k
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 32 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e final de lay tim e is de te rm ined b y the in te rnal delay time of the ic, the response t i me n eed ed for switch ing of f th e mosfet a nd the time -con st a n t, r17 c2 3. a min i mum rc time is required in order to filter ou t d i stur ba nces on pin fbsense. an rc time sele ction th at is to o lar g e can n o t follow th e ra mpin g up in pu t volt ag e pr op erly . the r e f o r e all o t h e r de lay s ar e f i rst s u b t r a c t ed fr om th e cond ucting tim e o f th e flyback mosfet . t he r e ma ining tim e shou ld b e at lea s t 5.5 time s the minim u m rc time re quir e d fo r filteri ng o u t disturbances on the fbsense . a common value for the internal delay time of the ic is 220 ns. switching of the mosfet usually takes around 60 ns (but check this value in the final application, as the situation might be different because of the use of different mosfets, gate resistors, etc). the conduction time of the flyback mosfet is shor test when the input voltage is at its highest. the highest value is usually 390 v (dc). equation 24 sh ows the cal c u l ation for r17 c2 3: (24) examp l e calculatio n fo r a typ i ca l 90 w a d a p ter : a c o mmonly used rc time for this filt er is 220 n s at r17 = 1 k an d c2 3 = 2 2 0 p f . this va lue is th er e f or e us ed f o r th e fo llow i ng eq uation s . the outpu t follo ws th e inp u t with a d e lay of ju st on e rc time af ter ro ugh ly five rc tim e s. th e tot a l de lay tim e ca n no w be ca lcu l at ed wit h eq uatio n 2 5 : (25) examp l e for a typical 90 w ada pter : t h e va lu e of r1 6a ca n no w b e ca lcu l at ed w i th eq uation 2 6 : (26) examp l e for a typical 90 w ada pter : r1 7 c 2 3 ns () l p i pmi n 39 0 10 9 ? --- ---- --- ---- ---- ---- --- - t int . del ay t m o sfet off ? ? ? 5. 5 -- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- --- - r1 7 c 2 3 45 0 10 6 ? 1.51 4 39 0 10 9 ? --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- - 220 6 0 ? ? 5. 5 -- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- -- - 29 3 ns ? t dela y t in t . delay t m o sfet off ? r1 7 c 2 3 ++ = t dela y 220 10 9 ? 60 1 0 9 ? 11 0 3 22 0 10 12 ? 500 ns = ++ = r1 6a 1 r co mp 83.33 3 10 6 - ---- ---- ---- ---- --- ---- ---- -- - ? ?? ?? ?? r sens e r com p t delay l p -- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- -- - ?? ?? = r1 6a 1 9.3 10 6 83.33 3 10 6 - ---- ---- ---- ---- --- ---- ---- -- - ? ?? ?? ?? 0.100 0 9.3 11 0 6 500 10 9 ? 450 10 6 ? -- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- - ?? ?? ?? 91 8 = =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 33 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 5.1 . 6 c alcu lation of the flyba ck sof t st art com ponent s the sof t st art is implemented thr ough the rc network at pin fbsense. th e sum of r1 6, r1 6a and r17 must b e at le ast 1 6 k ( se e tea17 52t _l t dat a sh eet ). th is en su re s that th e vo lt age v st a r t ( sof t ) f b (0 .6 3 v) is re ached a nd the st art- up of th e flyba c k is ena bled . in ge ner al the valu es o f r16 a a nd r17 a r e m u ch sm aller th an the valu e of r1 6. th er efor e th e sof t st ar t time is: . it is re co mme nde d to make the so f t st ar t time for th e fl yb ack lo nge r than th e sof t st ar t time o f the pfc. it is also re comme nd ed to ke ep the so f t st ar t time with i n the r ang e of 5 m s to 10 m s . th e tot a l sof t st a r t time is ap pr oximately 8 m s wh en c10 = 56 n f a n d r16 = 49 k . 5.2 f lyback control and pfc with delay op tions the flyback controls the operation mode of the pfc. the pfc is turned on at an internal flyback frequency of 86 khz and it is turned off at an internal frequency of 48 khz (see figure 12 and the tea1752t_lt data sheet ). pfc has a relatively fast turn-on, but its turn-off is delayed via capacitor c24, whic h is connected to the pfctimer pin (see figure 17 ). in this wa y it i s p o ssible to pr even t the pf c fr om en te rin g a kind of bu rst mo de b e cause o f fast an d subst a n t ial re petitive l o a d ch an ge s at th e ou tp ut . p r e v e n tin g th is r e sult s in a mor e st able inpu t volt a ge for the flyba c k. t he a m ou nt o f time for ig nor ing th e shu t ting d o wn sign al of the pf c de pe nds on the cap a cit a nce va lue con n e c ted to the pfctimer pin. this time can be calculated with equation 27 : (2 7) examp l e: a ca p a ci t ance valu e of 2 . 7 f fo r c24 re sult s i n a dela y of ap pr oximately 1 s . it is r e com m en ded to u s e a m i nimu m va lue of 1 n f for c24 . it is a l so r e com m en ded to pla c e the 1 0 nf no ise filter ca p a ci to r c15 as clo s e as p o ssible to the fbctrl pin to gu ar an te e a smo o th tr an sition fr om pfc-o f f to pfc- on a n d to avo i d aud ible n o ise in the flyb ack transformer . note that the hysteresis between turning on and turning off the pfc can be influenced by the inductance value (see section 5.1.2 ). also the valley time and other disturbances on the fbctrl pin makes the hysteresis smaller. it is therefore advised to use the layout guidance (see section 7 ) a nd kee p th e va lley tim e sh or t ( u suall y a value clo s e to 1 . 1 s lea d s t o go od r e s u lt s ) . 5.2 . 1 i mp rov i ng st a r t-u p time of the pfc th e pfc in th e tea175 2 is tur n e d on whe n th e flyb ack is su dde nly hea vily loa ded b y a step loa d . it is in ge ne ra l tur n e d on fast e nou gh , bu t some times an even sh or te r st art- up time is required. this is espec i ally valid at very low line volt ages in combination w i th large lo ad chan ge s. the flyba c k m a y ente r th e safe re st art mod e when th e maximu m o n - t im e pr o t ec tio n (t on (fb ) ma x ) is h i t be ca use of a volt ag e th at has be co me too low acro ss the b u lk e l ca p. se lectin g a lar g e r value fo r th e bu lk elca p and /o r st ar tin g up the pf c as so on a s possible improves this situation. figure 18 shows an example of how this can be done. t sof t sta r t 3r 16 c1 0 t dela y pfc of f ? c2 4 3 6 10 4
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 34 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e de lay time o f the pfc (d escrib ed in section 5 .2 ) is no longer determined by the value of c24 in figure 18 , but by c2 5. t he value o f cap a citor c24 has to be v e ry s m all, typically 1 n f . the st ar t-up time o f the pfc ca n be ne glec ted . it is r e comm end ed to use a tra n sistor with a lar ge dc cur r e n t gain ( = h fe ). the start-up time of the pfc in figure 17 is determined by equation 28 : (2 8) examp l e: a capacitance value of 2.7 f for c24 results in a delay of 18.7 ms before the pfc is turned on. the ratio between the turning off and the turning on of the pfc (in figure 17 ) th er ef or e eq u a ls 5 2 . 5.3 flyback protection mo de 5.3 . 1 s hort circui t on pin f b ctrl if p i n fbctrl is shor ted to gr ou nd, switching o f the flyback co ntro ller is inhib i ted. this situ a t io n eq ua ls th e m i n i m u m o r a no o u t p u t po we r s i tu at ion . 5.3 . 2 o pen fbctrl pin as sh own in figu re 1 9 . th e fbctrl pin is co nne cted to a n inter nal volt a ge sou r ce of 3 . 5 v via an in te rna l resistor o f 3 k . whe n th e volt ag e on p i n fbctrl exce ed s 2 . 5 v , this co nne ctio n is d i sa bled a n d the f b ct rl p i n is b i ased with an in te rna l 30 a current so ur ce . w h e n th e vo lt ag e on t h e f b ct rl p i n ex ce ed s v to (f bctrl ) (4.5 v) a fault is a s sum ed. switchin g of th e flyba c k (a nd a l so th e pfc) is b l ocke d an d the contr o lle r en te rs the sa fe r e st ar t mo de ( t ea17 52t ) or tr igge rs th e latched p r o t e c tio n (tea1 752 l t ). an internal s witc h pulls the fbctrl pi n do wn w h e n th e flyb ac k is dis a b l e d . 5.3 .3 t ime-out fl yback control loop a tim e - out fu nction can b e re alized to pr otect a gai nst an o u tpu t shor t cir c u i t a t initial st ar t- up o r aga inst a n o p e n co ntro l lo op situ at ion. this ca n be do ne by p l acing a r e sisto r in ser i es with a cap a citor b e tween p i n fbctrl and gro u n d . t he trig ger ing o f the time -o ut p r ote c tion g e n e ra te s a safe r e st ar t for the tea175 2t an d a latched pro t e c tio n fo r the tea1752l t . fi g 17 . s t an d a r d co nfi g u r ati o n for the pfctim er pin fig 18 . i mp ro ving th e st art-u p time o f th e pfc 019aaa04 8 2 tea1752 c24 pfctimer gnd 14 tea1752 r28 r29 15 k 150 q3 c24 c25 pfctimer gnd 14 2 019aaa049 t dela y pf c on ? 6 930 c 24 =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 35 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller when the voltage on pin fbctrl exceeds 2.5 v (see figure 19 ) the switch in series with the resist or of 3 k is ope ne d. pin fbctrl a nd ther ef or e the rc com b ina t io n is b i ased with a 30 a cu r r e n t so ur ce . w h e n th e vo lt ag e on p i n f b ct rl e xce ed s 4. 5 v , th e switchin g of th e flyba c k (a nd a l so o f the pfc) is blocked a nd the con t r o lle r en te rs th e sa fe r e st ar t mo de ( t ea175 2t) or is latch e d ( with t ea1 752 l t ). the cap a citor ca n be u s e d to set th e tim e fo r r eachin g 4.5 v at the fbct rl pin . t h e re sist or is necessary to s e p a rat e the relatively large time - o u t ca p a cito r fr om th e con t r o l loop r e spon se. it is advised to u s e a r e sisto r of at le ast 3 0 k . this res i stor also influences th e ch arg e time of th e cap a cito r . the time-out time t to can be calculated with equation 29 : (2 9) the capacitor can be calculated with equation 30 : (3 0) the resistor can be calculated with equation 31 : (3 1) examp l e with the fo llowing a s sum p tions: ? t to =3 7m s ? c to =3 3 0 n f if time-out protection is not required, if can be disabled by placing a resistor of 100 k between pin fbctrl and ground. t to c to v to fbctr l () i o fbctrl () r to ? () ? ? i o fbctrl () - ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- --- - = c to i o fbctrl () t to ? v to fbctrl () i o fbctrl () r to ? () ? ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- --- - = r to v to fbctrl () i of b c t r l () --- ---- ---- --- ---- ---- ---- -- - t to c to -- ---- - - ? = r to 4. 5 v 30 a --- ---- ---- --- - 37 ms 330 nf -- ---- --- ---- ---- - ? 37.9 k 39 k ==
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 36 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 5.3 .4 o vervolt a ge protecti on flybac k th e ic ha s an inter nal latche d over vo lt ag e protectio n circuit, which switche s o f f both con t r o lle rs whe n an over volt a ge is d e tected at t h e ou tp ut of t h e flyb a ck. t h e ic c a n de te ct a n over vo lt age at a seco nda ry win d in g of th e flyba c k by mea s u r in g th e volt ag e at th e auxiliary windi ng during the se condary stroke. a se ries resis t or bet ween the auxiliary wind i ng a nd the fbaux p i n conver t s this volt ag e to a cu rr en t thr oug h th e fbaux p i n . a. c i r cu it d i ag ra m b. t i mi n g di a g r am f i g 1 9 . t i m e - o u t prot ec tio n 019aaa043 fbctrl 3 2.5 v 4.5 v 30 a 3 k 3.5 v time-out tea1752 019aaa04 4 4.5 v 2.5 v v fbctrl output v oltage intended output v oltage not reached within time-out time . intended output v oltage reached within time-out time . restart fig 20. flyback ovp and opp circuit tea1752 r-ovp = r23 r-opp = r23 + r23a c13 d5 d_output t1 secondar y auxiliar y pr imar y r23 r23a d23a 019aaa045 gnd fba ux v cc 2 1 4
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 37 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller at a current, i ov p( fba u x) , of 300 a into the fbaux pin, th e ic de te ct s an o v e r vol t age . an in te rn al integr ator filter s n o ise an d vo lt ag e sp ikes. th e outp u t o f the in te gr ator is used a s a n in put fo r an up -do w n co unter . th e co unter h a s b een a dde d as an e x tr a filter to pr event false ovp de te ctio n, which mig h t occu r du rin g esd or lightnin g even t s . if the in te gr ator d e tect s a n over volt ag e, th e co unte r incre a ses it s valu e by 1 . if a nothe r o v e r volt a ge is d e tected du rin g th e ne xt switch ing cyc le, the counter inc r eas e s it s value by 1 a gain . if n o over vo lt ag e is de te cte d dur ing th e next switch ing cycle , the cou n ter sub t r a ct s it s value by 2 ( t h e m i nimu m valu e is 0 ) . if th e va lue re aches 8 , th e ic a s sum e s a tru e over volt ag e an d activate s the la tche d pr otecti on. both co nver te rs ar e switched o f f imm edia t e l y a nd v cc st ar t s cycling be twe en v th (uv l o) a nd v st a r t u p with out a re st a r t. switch ing of f a n d the n switching on the ma ins inpu t volt a ge trig ger s the fa st latch rese t cir c u i t and r e s e t s th e lat c h . th e ovp level can be se t by th e re sistor r ov p : (3 2) wh er e: ? n s is th e num ber of tur n s on the seco nda ry win d in g . ? n au x is the number of turns on the auxiliary winding of the flyback trans f ormer . ? v cla m p( fbau x) is th e po sitive cla m p volt a ge of the fbaux p i n. ? v f( d23 a ) is th e fo rw ar d vo lt a g e of d2 3a at a cu rr en t of 3 0 0 a. t h e to le ra nc es o n i ov p( fba u x) ha ve to t a ken into a c cou n t fo r th e calculatio n of the v ov p( vos e nse ) le ve l t o avo i d tr igg e r in g of th e ovp du r i ng n o r m a l o p e r a t i on . 5.3 . 5 o verpowe r protec tion (opp) th e maximu m outp u t p o wer in a flyba c k in qu asi-r e son ance mo de d epe nd s on th e ( m ain s ) inpu t volt a g e . an opp is imple m en te d to co mpe n sate for this. du rin g th e pr ima r y stroke of the flyback the mains volt age is se nsed by me asur ing the cur r e n t d r a w n fr om pin fbaux. with a resis t or between the fly b ack auxiliary winding and pin fbaux the v o lt age at the auxiliary winding is conv erted to a current i fba u x (see f i gur e 20 ). the ic uses the current information to reduce the setting of the maximum flyback peak current measured through pin fbsense. see figure 21 for the limitation of the maximum v fbsense level as a function of i fbaux . r ovp n aux n s - ---- --- -- - v ovp v osense () ?? ?? v clam p fbau x () v fd 2 3 a () ? ? i ovp fbaux () ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- - - = n aux n s - ---- ---- - - v ovp v osense () ?? ?? 0.7 typical () ? v fd 2 3 a () ? 30 0 a typical () - --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- -- =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 38 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller th e tot a l opp re si st a n ce de te rmin i ng the i fb aux cu rr ent dur ing th e pr imar y stroke o f the flyback exist s of r23 + r23a (see figu re 2 0 ). th e ovp r e sisto r r23 h a s to be ca lcu l ated b e for e th e re main ing p a r t of the o pp re sistor r2 3a ca n be calcula t e d . the value of r23a can be calculated with equation 33 : (33) th e sum of r2 3 an d r2 3a sh ou ld be lowe r th an 6 66 k . fig 21. o pp maximum fbsense volt age ? 360 ? 100 019aaa04 6 0.65 0.46 0 i fbaux ( a) v fbsense (v) r2 3a n aux n p ---- ---- -- - v o pfc () ? () ? i start o pp () --- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- -- - r ov p ? n aux n p - ---- ---- - - 24 0 v0 . 8 v ? ? ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- - r ovp ? ==
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 39 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 6. summary of calculations fo r adjustment of the flyback see figure 1 ap p lica t ion s c h e m a tic for c o m p on en t re fe re nc e nu m b e r s . fbsense has two intern al referen c e level s : (1 ) v st art(sof t )fb = 0 .6 30 v at dv/d t = 0 m v/ s (2 ) v se ns e ( fb )mi n = 0 .3 00 v at dv/d t 0 mv/ s a . most impo rt an t compo nent s for ad ju sting the flyback in the app licatio n l p =f ( p o ) assumptions: minimum volt age across buf fe rcap (c3) is appr oximately 100 v (d c) at 50 % of the nominal o utput powe r . (1 ) n (v o +v f )=8 0 v (2 ) n (v o +v f )=9 2 v (3 ) n (v o +v f ) = 104 .3 v (4 ) n (v o +v f )=1 1 8v (5 ) n (v o +v f ) = 130 v b . indica tio n o f the accept abl e i nduct ance val ue, rel a ted to ou tp ut po wer a nd n (v o +v f ) fig 22 . m ost im port ant compo n e n t s a n d ind u c t a n c e v a lue for adjusting the flyba ck in th e ap plication c10 fbsense r16 l p q2 r sense r comp c23 r16a fbdriver r series = r17 + r16 v i (dc) r17 t1 c_output d_output 019aaa039 i adj(fbsense) (1) (2) (3) (4) 019aaa041 p o (w) 75 155 135 115 95 400 600 800 lp ( h) 200 (5)
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 40 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller step 1: use the graph in figure 22 to de te rm in e an in dic a t i on f o r th e pr im ar y in d u ct a n c e value or use equation 34 : (34) s t ep 2 : sele ct a tr an sfo rme r an d ca lculate the satur a tion cu rr ent: (3 5) s t ep 3: calcula t e th e re quir e d p eak cur r en t thr o u gh the flyback tr an sfor mer . ca lcu l ate this valu e dur ing n o min a l ou tp ut cu rr ent in comb i n a t ion w i th th e m i nim u m ele ctr oly t ic bu f f er cap a citor volt a g e a nd at pea k ou tp ut cu rr ent wh en the pfc is op er ating . on ly the hig h e s t valu e of th ese two n eed s to be t a ke n into accou n t. name th is value i pma x . (3 6) wh er e: ? a=n v i(d c ) m i n l p ? b= ? 2 i o l p {n (v o +v f )+ v i(dc) min } ? c= ? 2 i o t va l l e y n v i( dc) min (v o +v f ) common rule is that i p( sa t) >i pma x . se le ctin g th e hig h e r i p( sa t) va lue for i pma x pr ev en t s sa tu ra tio n of th e tr an sfo r m e r an d allo ws a po we r ma r g in . t h er ef or e in ge n e r a l th e calcula t io n is con t i nue d with i pma x =i p( sat ) . s t e p 4: ca lcu l at e i pmi n ( r e l ated to the tur n ing o n or the tu rn ing of f of the pf c) : (3 7) fb st an ds fo r th e ef ficie n cy o f the flyback. use relativ e ly high va lu es, e.g. close to 0. 97 ? 0. 98 . s t ep 5 : calcula t in g th e value o f r s ens e : (3 8) s t ep 6 : calcula t in g th e value o f r se ri es : (3 9) note that the r se r i e s com p r i se s two co mpo nen t s, r16 a nd r17. the co mmon va lue for r17 is be twee n 82 0 a nd 1 200 . a typical value th at is used o f te n is 1 000 . l p nv o v f + () 1 04.3 ---- ---- ---- ---- --- ---- ---- ---- - - ?? ?? 43 061 1 0 6 ? i o nom () v o v f + () () 1 . 0005 ? = i ps a t () n p b ma x a e l p -- ---- ---- ---- --- ---- ---- ---- ---- --- - = i pmax b ? b 2 4ac ? () + 2a ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- - - = i pmin 2 0 .3 75 i o nom () v o v f + () l p 67 000 fb --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- - = r sense 0.33 i pmax i pmin ? ---- --- ---- ---- ---- ---- --- ---- - = r se ri es i pmax 0.3 i pm i n 0.63 ? 31 0 6 ? i pmax i pmin ? () -- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- --- - =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 41 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller s t ep 7 : checking /calcu lating the time con s t a nt r1 7 c23: (4 0) wh er e: ? t in t.d el ay = 220 n s ? t mos f et -of f ? 60 ns ( n ote th at th e va lue can b e dif f er ent in othe r ap plications) in ge ner al the calcula t io n of ten sh ows tha t r17 c23 2 2 0 n s. if th is is so t h en 22 0 n s should be suf f ic ient for r17 c23. a s lightly smaller v a lue mi g h t b e a c ce pt ab le but is not p r efe r r ed ( has to b e checked o n th e ap plication b oar d) . s t e p 8: ca lcu l at e th e de lay t i m e : (41) remark: t he comm only used valu e for r17 c2 3 is 2 2 0 n s (see a l so step 7 ) . s t ep 9 : calcula t in g th e comp ensatin g resistor r comp : (4 2) calcula t in g the valu e of r 16 a : (4 3) r1 7 c 2 3 ns () l p i pmi n 39 0 10 9 ? --- ---- --- ---- ---- ---- --- - t int . del ay t m o sfet off ? ? ? 5. 5 -- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- --- - t dela y t in t . delay t m o sfet off ? r1 7 c 2 3 ++ = r co m p 2r 5 r 5 a r6a 2 - ---- ---- - - ++ ?? ?? = r1 6a 1 r co mp 83.33 3 10 6 - ---- ---- ---- ---- --- ---- ---- -- - ? ?? ?? ?? r sens e r com p t delay l p -- ---- ---- ---- --- ---- ---- ---- --- ---- ---- ---- ---- --- ---- -- - ?? ?? =
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 42 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 7. pcb layout considerations a goo d layou t is co nside r ed to b e an imp o r t an t p a r t of th e final de sig n . it minim i ze s al l kind s of distur ban ce s a nd ma ke s the o v e r a ll p e r f o rma nce mo re r obu st with le ss r i sk of emi. guidelines fo r the impr oveme n t of the la yout of th e pr int-circuit bo ar d ar e given below: ? separate large signal grounds from small signal grounds (see figure 23 ). sma ll sign al g r ou nd s can b e easily r e cog n ized b y the i r tria ngle sha p e d symb ol. all oth e r g r ou nd symbo ls ar e re lated to la rge sig nal gr ou nd s. ? t r y to ma ke th e pr int a r e a th at fit s wi th in th e sep a r a te lar ge sign al loop s (see figure 23 ) as small as pos sible. eac h sep a ra te la rg e sig n a l lo op ha s it s own color . ? th e conn ecti on be twe en bo th mosfet s ( p fc and flyba c k) a nd b o th dr ive r ou tput s of the ic sho u ld b e as sh or t as possible ( g r e e n line in fig u r e 23 ). t r y to minimize the cou p ling b e tween th ese two sign als b y in cr ea sin g the dist a n ce betwee n th em an d/or p r efer ab ly u s in g a gu ided g r o und tr ack for both con nections. ? th e powe r gr oun d and sma ll sign al gr ou nd ar e on ly conn ecte d with o ne shor t cop per tra c k (ma ke this tr ack a s sh or t an d as wid e as possible ) . pr efer ably it shou ld becom e o ne spot (con ne ction b e tween g r o u n d 4a an d gr ou nd 6a ). ? use a gr oun d shield u n d e rn ea th the ic, con n e c t th is gr ou nd shie ld to pin 2 of the ic. ? all re sistor s con nected in ser i es with a n i c p i n sh ou ld be c o n n e ct ed a s clos e as p o s s ib le to th at p i n. ? any he at sink co nne cted to a com pon en t mu st be con nected to that comp one nt's n ear est cor r e s pon ding gro u n d sig nal . ma ke this co nn ectio n as sh or t as po ssible . con nect th e hea t s i n k o f dio d e b r id ge bd1 to g r o u n d 1, q1 to 4 and q2 to 4b. in typical a pplica t io ns all th re e com pon en t s are o f te n mo un te d o n o n e single he at sink. if th is is in de ed t h e ca se , jus t m a ke on e wid e copp er t r a ck th at co nn e c t s a ll t h r e e g r ou nd s me ntione d ab ove to each oth e r . also co mbin e in this co ppe r tra c k gr oun d 2. ? con nect th e gr oun ds o f 6 b with e a ch othe r . ? ma ke a so -calle d "st a r gr ou nd " fro m gr oun d 6a , 6b , 6c, and 7 . gro und 6 a is the m i ddle o f the st ar a n d is co nne cte d to p i n 2 ( t h i s is th e gro u n d of th e ic) . ? grou nd s ma rked with 7 do n o t h a ve to be a so- c alled "st a r gr oun d? . ? place the y- ca p acro ss gr ou nds 1 an d 8. pr efer ab ly use on e special cop per tr ack, sep a r a ted fr om all othe rs fo r this co nne ct io n (o r use the con nection co p per tr ack o f the h eat sin k s in a typ i ca l a p p lica t io n setup for this pu rp ose) . ? c4 , c 1 5 , c23 a n d c 2 2 ( i n or de r of p r io rit y ) sho u l d be p l ac ed a s c l os e as po ss ible to the ic. red u ce co up ling be twe en the pf c s witching signals (pfc driv er and pfcaux ) and the flyback sense signal s (fbsense and fbctrl) as much as p o ssib le, becau se th is m i nimizes th e r i sk of electro m ag netic inter f e r e n ce an d au dible no ise . ? figure 23 sho w s an o v e r view of th e hier ar chy o f the d i f f er en t gr ou nd s at th e bo ttom . ? con nect th e ano de o f the tl 431 (gr o u n d 8 ) to gro u n d 9 with o ne spe c ia l sep a rate con necting cop per tr ack. min i mize all othe r cur r en t s in this spec ia l tr ac k. t h e ac tu al place of connection should preferably be loca ted as close as possible to the output.
x xxx xxx xxxx xxx xxxx xxx xx xxxx xxx xxxx xxx xxxx xxx xxx xxx xxx x x x x x xxxx xxx xxxx xxx xxxx xxx xxxx xxx x x xxxx xxx xxx xxxx xxx x xx xx xx xxx x xxx xxx xxxx xxx xxxx xxx xxxx xx xxx xxxx xxx xxxx xxx xx x xxx xx xxxx xxx xxxx xxx xxxx xxx xxx xxxx xxx xxxx xx xxxx xxx xxx x x x xxx xxx xxxx xxx xxxx xxx xxx xxx xxx xxxx xxx xxxx xxx xxxx xxx xx xxx xxx xxxx xxx xxxx xxx xxx xxxx xxx xxxx xxx xxxx xxx xxx xxxx xx xxxx xxx x x xxx xxx xxxx xxx xxxx xxx xxxx xx xxx xxxx xxx xxxx xxx x xx x AN10861 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 16 july 2010 43 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller f i g 2 3 . p cb layo ut co nsid eration s large signal current loop large signal current loop large signal current loop + ? mains inlet c12 c15 r24 c16 c17 c18 c19 u1 pfctimer gnd latch vinsense hvs v osense fbdriver fbsense hv v cc pfcsense pfcdriver pfca ux c20 c21 c22 c24 c25 r4 r25 r26 rt 2 ntc c14 c10 c23 c4 r7 r10 c6 r11 r27 r28 r29 q3 r3 r12 r9 c5 c2 c1 bd1 lf2 lf1 f1 r t1 ntc cx1 r1 r2 d1 bc1 r6 r14 r13 d4 d3 q2 r6a r18 r15 r17 r5a r5 r16 r16a q1 r8 d2 7 1 9 12 tea1752 c13 r20 r37 r38 r35 r34 fbctrl fba ux pfccomp r23a r23 d23a d5 c9 c8 c3 t1 l2 l1 5 1 4 2 6 c35 c34 r36 u2 u4 1 2 4 4 14 11 12 8 7 15 9 13 10 16 1 25 3 6 3 019aaa047 cy1 bc2 u3 v cc c30 r30 q4 r32 c27 c28 c29 r33 c31 l3 d30 11 7, 8 9, 10 8 2 3 5 6 7 driver srsense v out + v out ? n.c. n.c. n.c. n.c. 41 gnd tea1791 optional see section 5.2, 5.2.1 1 23 6 c 4a 4 4b 77 7 6 b 6 b 6a 7 7 7 7 7 7 7 777 7 7 9 6b 8 8 1 1 3 4 4a 4b 8 9 6a 6b 6c 7 2
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 44 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 8. references [1] iec-60950 ? chapter 2.1.1.7 ?discharge of capacitors in equipment?
a n 1086 1 a l l info r m atio n pr ov ide d in thi s d o cu ment is su bje c t t o le gal dis c l a i m er s. ? nx p b . v . 201 0. al l r i ght s r e se r v ed. application note rev. 01 ? 16 july 2010 45 of 46 nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller 9. legal information 9.1 definitions dr a f t ? the do c u m e nt is a draf t versi on onl y . the cont ent is st ill unde r int e rn al review and subje c t to f o rmal ap proval, which m a y re su lt in modif i cat i ons or add itio ns. nxp se miconduct o rs does not g i ve a n y rep resent a t io ns o r wa rrant ies as t o t he accu racy or compl e te ness o f inf o rma tio n in c l u ded her ein and shall hav e no liab ilit y fo r t he consequ ences o f use of such inf o rmat i on . 9.2 disclaimers li mi te d wa rr a n ty an d li a b il it y ? i n f o rmat i on in th is documen t is bel ieved to be accurat e and re liabl e. however , nxp s e micondu ct ors doe s not give any rep resent a t io ns o r wa rrant ies, e x p ressed or implie d, as to t he accuracy or completen e ss of such informa tio n a nd shall have no lia bility for the consequ ences o f use of such inf o rmat i on . in n o e v e n t shall nxp s e micond uctor s be lia ble fo r a n y in dire ct , in cid ent a l , pun itive, spe c i a l or consequ ent ial damag es (inclu ding - wit hou t limit a t io n - lost prof it s , lost savings, business int e rrupt ion, cost s related t o the remov a l or rep l acement of an y pro duct s o r rework ch arge s) whe t he r or not such dama ges a r e based on t o rt ( i ncludi ng negli gence) , warra nty , bre a ch of cont ract or an y ot her le gal th eory . not with s t andin g a n y d a mages th at cust omer might incur fo r any r eason what soe v e r , nxp semi co nduct o rs? ag greg at e and cumulat i ve l i abil i ty t o ward s custome r for t he pro duct s d e scr i bed he rein shall be li mite d i n a c cor dance wit h t he t e rms a nd condit i on s of comme rcial sale of nxp s e micondu ct or s. ri ght to m ake c h a n ge s ? nx p semicon ducto rs re s e rves t he rig h t t o ma k e chang es t o inf o rmat i on pu blished in t h is documen t, in cludin g wit ho ut limit a t io n sp ecificat ion s an d p r odu ct descript i ons, a t any time a nd with out not ice. this documen t super sed e s a nd repla c e s all inf o rma tio n sup p lied pr ior to t he pu blicat ion her eof . s u it a b il it y f o r us e ? nx p semicon ducto rs pr oduct s are no t design ed, aut hor ized or warran t e d t o be suit a b le fo r use i n l i fe supp ort , lif e-crit ical or safe ty-crit i cal syst ems o r e quip ment , nor in ap plicat ions where f a ilu re or malf unct i on of a n nx p semicond ucto rs pr oduct can re asonab ly be expe ct ed to result in per sonal inju ry , d eat h or seve re prop ert y or envi ronme n t a l damag e. nxp s e micondu c t ors accept s no liab ilit y f o r inclusion an d/o r use o f nxp semicon duct o rs p r odu ct s in such equip m ent o r a pplicat ion s and th eref ore such inclusion a nd/ or use is at the cust omer ? s own risk. ap plic ation s ? a ppli c a t io ns t hat a r e describe d h e rei n f o r an y of t hese prod uct s ar e for il lustra tive pu rpos es only . nxp se mico nduct o rs makes no repr esent a t io n o r wa rran t y tha t such a pplication s will be suit a b le for the sp ecifi ed use w i tho u t f u rt her t e sti ng or modif i cat i on. custome r s ar e responsib le for t he desig n a nd ope rat i on of t hei r a pplicat ion s and pr oduct s using nxp s emicondu ct or s pro duct s, an d nxp semi co nduct o rs acce pt s no liabi lity fo r any a s sist a n ce wit h app licati ons o r cu st omer pr oduct design . it is cust omer ? s sol e r e sponsib ilit y t o d e t e rmine whe t he r t h e nxp semicon ducto rs p r odu ct is sui t able a nd f i t f o r t he custome r ? s a pplicat ion s an d prod uct s pl anne d, as well as f o r t he plan ned app licati on and use of cu st ome r ? s t h ird p a rt y cust omer( s ) . custo mers sho u ld pro v id e appro p ria t e design an d o pera t in g saf e g uard s t o min i mize the r i sks asso cia t e d wit h t heir appl ica t io ns a nd prod uct s. nxp semicon duct o rs d oes n o t accept any liabil i ty rela ted t o any def ault , damag e, cost s o r probl em wh ich is based on a n y weakne ss or def aul t in th e cu st ome r ? s ap plicat ions or prod uct s, or t he appl ica t io n o r use b y custo m er ? s th ird p a rt y custo m er(s). c u st omer is respo n sible f o r doing a ll n e cessa r y te st ing f o r th e cu st omer ? s app lic at ions and pro duct s u s i ng nxp semicon ducto rs p r oduct s in orde r to av oid a de fau l t of the ap plicat ions and the p r odu ct s or of t he applicat ion or use by cu st omer ? s t hird p art y cu st ome r(s). nxp d oes n o t accept a n y lia b ilit y in t h is r e sp ec t. export c o nt r ol ? thi s docume n t as well as t h e it em(s) describ ed here i n may b e sub j ect t o e x p o rt con t ro l r egul atio ns. expo rt migh t requ ire a prio r aut hori z a t io n f r o m na tio nal aut hor iti e s. 9.3 t r ademarks noti ce : all r e fe renced b r ands, prod uc t name s , service names and t rad emarks are t he prop ert y of the i r respect i ve o w ners. gr een ch ip ? is a tr ade mark o f nxp b. v .
nxp semiconductors AN10861 greenchip iii tea1752 integrated pfc and flyback controller ? nxp b . v . 20 10 . a l l r i g h t s re se rv ed. for m o r e i n for m a t i o n , plea se visit: htt p :// w ww.n x p.co m for sale s of fice a d d r e sses, plea se se nd an ema i l t o : s a lesa ddre sses@ nxp . com date of release: 16 july 2010 document identifier: AN10861 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 10. content s 1 i n trod uctio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 t he tea1 752 gre enchi p iii co ntrolle r . . . . . . . 3 1.2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.2 system features . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.3 pfc feat ur es . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.4 flyback f e atures . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 application schematic . . . . . . . . . . . . . . . . . . . . 4 2 pi n d e scrip t io n . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 system descrip t io n an d calcu l atio n. . . . . . . . . 8 3.1 pfc and flyback st art c o ndit i ons . . . . . . . . . . . 8 3.2 s t a r t-up se quen ce. . . . . . . . . . . . . . . . . . . . . . . 8 3.3 v cc cycle in safe rest art protection mode . . . . 10 3.4 main s vol t a ge sensin g and bro w nou t . . . . . . . 1 1 3.4.1 dis charge of m a ins input cap a citor . . . . . . . . . 1 1 3.4.2 brown out vo lt age ad justme nt . . . . . . . . . . . . . 1 2 3.5 internal overtemperatur e protection (otp) . . 1 2 3.6 la tch pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 fast lat ch reset . . . . . . . . . . . . . . . . . . . . . . . . 13 4 pfc d escr ip tio n an d ca lc ulation . . . . . . . . . . 1 3 4.1 pf c o u tput p o wer an d vo lt a ge control . . . . . . 1 4 4.1.1 setting the pf c out p ut volt age . . . . . . . . . . . . 15 4.1.2 ca lcula t io n of the pf c so f t st art a nd sof t stop component s . . . . . . . . . . . . . . . . . . . . . . 17 4.2 pf c d e magn etizing an d valle y de te ctio n . . . . 1 7 4.2.1 de si gn of the pf caux wind i ng an d ci rcuit . . 1 8 4.3 pf c p r ote cti on modes . . . . . . . . . . . . . . . . . . 1 9 4.3.1 vosen s e ove r vo lt a ge protection . . . . . . . . . 1 9 4.3.2 vosen s e op en and sh ort pi n d e tection . . . . 1 9 4.3.3 vinsense o pen pi n detection . . . . . . . . . . . . 2 0 4.3.4 overcurrent protect i on . . . . . . . . . . . . . . . . . . 20 5 f l yback descrip t io n an d calcu l atio n . . . . . . . 20 5.1 f l yback outpu t pow er co ntrol . . . . . . . . . . . . . 2 0 5.1.1 t h ree di f f ere n t o peration mod e s of the t ea1752 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 5.1.1.1 quasi-resonant mode . . . . . . . . . . . . . . . . . . . 22 5.1.1.2 di sco n tinuo us co ndu ctio n mo de . . . . . . . . . . . 2 3 5.1.1.3 f r eque ncy re duction mod e . . . . . . . . . . . . . . . 2 3 5.1.2 t he rela tio n shi p b e tween induct ance val ue and t h e hyst er esis of the pf c . . . . . . . . . . . . 24 5.1.3 re lation sh ip be twe en i pmi n and the req u ired pfc-on/of f level . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.4 t he influ ence of r sen se a nd th e series resist ance r16 + r17 . . . . . . . . . . . . . . . . . . . 28 5.1.4.1 ca lcula t in g th e sa tu rati on current i p( sa t ) of t h e f l yback transformer . . . . . . . . . . . . . . . . 28 5 . 1 . 4.2 ca lcula t i on of i pm ax for flyback ope rating in quasi - re sonan t mode . . . . . . . . . . . . . . . . . . 29 5. 1. 4 . 3 c a l cu l at io n o f th e cu rren t se ns e res i st or r se ns e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 . 1 . 4.4 ca lcula t i on of the seri es re sist an ce r16 and r17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 . 1 . 5 ca lcula t i on of the d e lay compen sation resistors r co mp and r16a . . . . . . . . . . . . . . . 31 5 . 1 . 6 ca lcula t i on of the flyba ck sof t st art co mp onen t s . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 . 2 f l yba c k control an d pfc with del ay options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5. 2. 1 improving s t art-up time of the pf c . . . . . . . . 33 5. 3 flybac k protection mode . . . . . . . . . . . . . . . . 34 5. 3. 1 short circuit on pin fbctrl . . . . . . . . . . . . . 34 5. 3. 2 open fbct rl pin . . . . . . . . . . . . . . . . . . . . . 34 5. 3. 3 t i m e -out flyback cont rol loop . . . . . . . . . . . . . 34 5. 3. 4 overvolt age protect i on f l yback . . . . . . . . . . . . 36 5. 3. 5 overpower protection (op p ) . . . . . . . . . . . . . 37 6 sum m ary o f c a lculation s for ad justme nt of th e flyback . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 pcb l a you t co nsid eratio ns . . . . . . . . . . . . . . 42 8 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 leg a l in fo rmatio n . . . . . . . . . . . . . . . . . . . . . . 45 9. 1 def i nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9. 2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9. 3 t r ademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 con t ent s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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